Detection and Analysis of Hardware Trojans in Digital Adder Architectures

Abstract

Globalization of integrated circuit (IC) manufacturing has made the implementation of malicious modifications, otherwise known as hardware Trojans, a physical challenge to the integrity and security of arithmetic units. Adders, which form a key element of most digital subsystems, are particularly sensitive to such attacks. This paper explores the impact of information-leakage and function-destructive Trojans inserted into the framework of a 13-transistor hybrid full-adder architecture. The Trojans make use of an AND-based trigger coupled with an XOR-based payload; their impact is measured through complete simulations run in a 45nm CMOS process under a 1V supply voltage. It has been found that, upon insertion of the Trojan, large degradations occur in key performance metrics such as power dissipation, which increases by 0.79 μW to 2.04 μW, and propagation delay, which can increase by 0.02ns to 49.72ns. Trojan-infected adders have a much higher power consumption than the nominal design and can consume multiple times more power than the nominal design, depending upon operating conditions. Thermal analysis shows increased power consumption, with the highest power consumption being 4.85mW at 75 °C. The same tendencies can be found in both slow slow (SS) and fast fast (FF) configurations, giving an impression of the sensitive nature of Trojan-affected adders to process voltage temperature (PVT) variations. These results provide a thorough assessment of the vulnerability of hybrid adders to hardware Trojans and highlight the need to strengthen the detection and countermeasures in the design of arithmetic circuits.