A Low Power and Area Efficient Leading Zero Counter

Abstract

The latest and up-to-date arrangements for arithmetic logic units are necessary for modern processors to function effectively. Leading zero counters (LZCs) are indispensable for floating-point operations because they accelerate computational throughput and allow for
parallel processing. Advancements in ASIC technology have enabled the development of LZC systems that process information rapidly and use very little energy. The high-speed, energy-efficient performance of Application Specific Integrated Circuits (ASICs) is why they
are preferred for creating LZCs in modern computer systems. By reducing the number of transistors required, the proposed LZC architecture results in smaller area and power consumption than other embedded multiplier designs. Of the four techniques, the 32-bit
LZC results in a 28.72% space reduction and a 16.44% decrease in power consumption. Similar to 64-bit LZC, the design achieves a 27.65% reduction in area and a 21.64% reduction in power consumption. These changes cause only a small increase in delay compared
to LZC done in the past. The design was implemented using Verilog Hardware Description Language (HDL) and processed using the Xilinx Vivado application on the 45 nm technology node. Consequently, the architecture is scalable and easily adapted to modern processing requirements. This architecture significantly reduces energy consumption, contributing to energy-efficient computing systems and supporting sustainable digital infrastructure.