10-bit 45.5-Ms/s Asynchronous Successive Approximation ADC with a Differential CDAC Switching Circuit in 45 nm CMOS

Alwin Thomas; A. Tressha; K.V. Priyadarshni; Gayathri K.M; Thangadurai N; Godfrey D

doi:10.31838/jvcs/08.01.14

Authors

Alwin Thomas Department of ECE, Dayananda Sagar University, Karnataka, India https://orcid.org/0009-0005-0831-6979
A. Tressha Department of ECE, Dayananda Sagar University, Karnataka, India https://orcid.org/0009-0006-7211-9176
K.V. Priyadarshni Department of ECE, Dayananda Sagar University, Karnataka, India https://orcid.org/0009-0004-2553-6554
Gayathri K.M Department of ECE, Dayananda Sagar University, Karnataka, India https://orcid.org/0000-0002-8299-8833
Thangadurai N Vinayaka Mission’s Research Foundation (Deemed to be University), Salem, India https://orcid.org/0000-0002-2149-9440
Godfrey D Department of ECE, Dayananda Sagar University, Karnataka, India https://orcid.org/0009-0006-1964-1125

DOI:

https://doi.org/10.31838/jvcs/08.01.14

Keywords:

Asynchronous SAR ADC, Low-power design, Capacitive DAC, Dynamic comparator, CMOS

Abstract

A 1.2 V 10-bit asynchronous successive approximation register (SAR) constructed with CMOS technology and an analog-to-digital converter (ADC) are proposed here in this study. An internal clock generator, a capacitive digital-to-analog converter, a sample-and-hold switch, SAR Logic, and a dynamic comparator form the asynchronous SAR ADC system. A maximum of ENOB for a sampling frequency of 45.5 MHz is 9.5 bits, the signal-to-noise ratio of which is 58.9 dB, while the overall power consumption is 167.16 μW, calculated based on a 64-point FFT of the Successive Approximation ADC’s output and input signals of 1.2 V differentially. The figure-of-merit obtained by Walden’s calculation is 14.5 fJ/step. Applications where low power, medium resolution, and medium speed are primarily required, for example, computing-in-memory cores for artificial intelligence and sensors used for biomedical applications, can employ this SAR ADC system.