Physics-Informed VLSI TinyML-Based Self-Healing PLL with Power–Jitter Optimization Under Aging and PVT Variations

Abstract

Phase-locked loops (PLLs) are essential components for generating frequency signals in today’s systems on a chip, but their overall jitter, stability, and behavior in terms of being ‘locked’ to each other can be affected by the varied manufacturing process, operating
voltage, and temperature, and long-term aging of the devices as well as other factors (e.g., supply chain issues, etc.). PLLs use feedback to regulate the output frequency, and any of the aforementioned types of variability can result in less-than-optimal characteristics
(e.g., loop gain, VCO sensitivity, charge pumps, etc.), thus causing PLLs to drift away from the intended damping and bandwidth; therefore, increasing RMS jitter or forcing conservative guard banding that wastes power. Recent research has demonstrated the continued development of PLL architectures/calibration techniques and how critical it is that, as semiconductor technology continues to scale down, sufficient attention will be paid to ensuring that the PLL user’s dynamic performance remains robust, given the continued variability and reliability issues associated with technology scaling. Additionally, studies on aging have shown that mechanisms like BTI have measurable effects on charge pump operation, underscoring the need for lifetime-based compensation methods rather than fixed margins. This study proposes a physics-informed TinyML self-healing PLL that utilizes (i) on-chip monitors, (ii) a compact TinyML estimator to provide a near-optimal initial knob setting, and (iii) a constrained local refinement stage that enforces power budgets and stability/transient constraints expressed through ζ, wn, resonant peaking Mr, and settling time ts. We formulate runtime tuning as a constrained multi-objective optimization over ICP and loop bandwidth BW. A simulation-centered evaluation using a behavioral CP-PLL model augmented with stochastic PVT spread and aging degradation spans T ∈ [–20,100]ºC, VDD ∈ [0.85, 1.15]V, and aging a ∈ [0, 7] years will be performed with the goal of demonstrating that the proposed method will achieve a significant and consistent reduction in jitter across 1200 random operating conditions for the represented device under the constraints
imposed and enforced; conversely, it will be demonstrated that jitter reduction based purely on TinyML decision making will have nonzero violations related to the constraints imposed. The results of the evaluation will demonstrate the practicality of using compact
learning in combination with physics-based feasibility checks to achieve predictable self-healing behavior suitable for VLSI clocking subsystems.