[1]
Kumawat, R., Dua, T., Singh, N., Sharma, J. and Srinivasulu, A. 2025. High Speed Energy Efficient Latch Architectures for Sequential Circuit Design. Journal of VLSI Circuits and Systems. 7, 1 (Mar. 2025), 56–65. DOI:https://doi.org/10.31838/jvcs/07.01.08.