Birla, S., Neha Singh, Jeevani G.S.N, Kumawat, R., & Srinivasulu, A. (2025). Unified Multimodal 64-Bit Arithmetic Logic Unit for High-Performance Computing Architectures. Journal of VLSI Circuits and Systems, 7(2), 1–8. https://doi.org/10.31838/JCVS/07.02.01