G, R.; D, V.; M, A. Development of Synthesizable Filter-Centric Loop Filter Design for ADPLL Architecture in SoC. Journal of VLSI Circuits and Systems, [S. l.], v. 6, n. 2, p. 1–13, 2024. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/110. Acesso em: 28 sep. 2024.