CH, P.; C. PADMA; R. KIRAN KUMAR; T. SUGUNA; C. NALINI. Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits. Journal of VLSI Circuits and Systems, [S. l.], v. 7, n. 1, p. 40–45, 2025. DOI: 10.31838/jvcs/07.01.06. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/112. Acesso em: 3 apr. 2025.