GOPNARAYAN, S.; MARKANDE, S. Efficient Design of Up Sampler and Down Sampler using Single Electron Transistor-Metal Oxide Semiconductor Field Effect Transistor. Journal of VLSI Circuits and Systems, [S. l.], v. 7, n. 1, p. 32–39, 2025. DOI: 10.31838/jvcs/07.01.05. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/152. Acesso em: 3 apr. 2025.