U. G. PATIL; PRABODH JAGTAP; KEDAR ADAKE; SANIKA DHANBHAR; AJAY PAITHANE. Efficient VLSI Architecture Integrating Vedic Mathematics for Square Computation. Journal of VLSI Circuits and Systems, [S. l.], v. 7, n. 1, p. 66–74, 2025. DOI: 10.31838/jvcs/07.01.09. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/157. Acesso em: 16 may. 2025.