KUMAWAT, R.; DUA, T.; SINGH, N.; SHARMA, J.; SRINIVASULU, A. High Speed Energy Efficient Latch Architectures for Sequential Circuit Design. Journal of VLSI Circuits and Systems, [S. l.], v. 7, n. 1, p. 56–65, 2025. DOI: 10.31838/jvcs/07.01.08. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/171. Acesso em: 3 apr. 2025.