SUPRIYA B K; ARUNRAJA A; BREMIGA GOPALAN GANDHIMATHI; S SHEEBA RANI; N SUDHAKAR REDDY; DEEPALI RANI SAHOO. DFT Aware Test Architecture for Communication ICs: ATPG- Based Fault Detection on Lower Technology Node. Journal of VLSI Circuits and Systems, [S. l.], v. 7, n. 1, p. 106–117, 2025. DOI: 10.31838/jvcs/07.01.13. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/187. Acesso em: 6 jul. 2025.