SIRISHA MALLAIAH; M VINODHINI. An Efficient Error Resilient Ternary Content Addressable Memory Architecture. Journal of VLSI Circuits and Systems, [S. l.], v. 8, n. 1, p. 1–8, 2026. DOI: 10.31838/JCVS/08.01.01. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/245. Acesso em: 27 feb. 2026.