BIRLA, S.; NEHA SINGH; JEEVANI G.S.N; KUMAWAT, R.; SRINIVASULU, A. Unified Multimodal 64-Bit Arithmetic Logic Unit for High-Performance Computing Architectures. Journal of VLSI Circuits and Systems, [S. l.], v. 7, n. 2, p. 1–8, 2025. DOI: 10.31838/JCVS/07.02.01. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/252. Acesso em: 9 jan. 2026.