TRI-DUC TA; NGUYEN, T.-P. N.; TRAN, Q.-T. T. Implementation of an Efficient RISC-V Processor Featuring a Novel Gshare Branch Prediction Technique. Journal of VLSI Circuits and Systems, [S. l.], v. 7, n. 2, p. 68–76, 2026. DOI: 10.31838/JCVS/07.02.08. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/259. Acesso em: 27 jan. 2026.