KOTHA GAYATHRI DEVI; KOTTAPALLI TEJASREE; MERUGUMALA KEZIA SWARNA SRI; MOPIDEVI PRAVALLIKA. Energy Reduction of D-Flipflop Using 130nm CMOS Technology. Journal of VLSI Circuits and Systems, [S. l.], v. 3, n. 2, p. 34–41, 2021. DOI: 10.31838/jvcs/03.02.04. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/32. Acesso em: 19 sep. 2024.