BRAHMAIAH BATTULA; PUTTA VIJAYA LAKSHMI; SANDINENI LAKSHMI NAVYA SRI; SUNANDA KARPURAPU; SIKHAKOLLI DURGA SRI SRAVYA. Design a Low Power and High-Speed Parity Checker using Exclusive–or Gates. Journal of VLSI Circuits and Systems, [S. l.], v. 3, n. 2, p. 48–53, 2021. DOI: 10.31838/jvcs/03.02.06. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/34. Acesso em: 22 dec. 2024.