VALLABHUNI VIJAY; CHANDRA S. PITTALA; K. C. KOTESHWARAMMA; A. SADULLA SHAIK; KANCHARAPU CHAITANYA; SHIVA G. BIRRU; SOMA R. MEDAPALLI; VARUN R. THORANALA. Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits. Journal of VLSI circuits and systems, [S. l.], v. 4, n. 01, p. 20–26, 2022. DOI: 10.31838/jvcs/04.01.04. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/39. Acesso em: 4 jul. 2024.