C, P.; R.V.S. SATYANARAYANA. Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications. Journal of VLSI Circuits and Systems, [S. l.], v. 6, n. 1, p. 7–18, 2023. DOI: 10.31838/jvcs/06.01.02. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/51. Acesso em: 27 nov. 2024.