MOHAMED ARSHATH. Detection Of Soft Errors in Clock Synthesizers and Latency Reduction Throgh Voltage Scaling Mechanism. Journal of VLSI Circuits and Systems, [S. l.], v. 6, n. 1, p. 43–50, 2023. DOI: 10.31838/jvcs/06.01.07. Disponível em: https://vlsijournal.com/index.php/vlsi/article/view/89. Acesso em: 22 dec. 2024.