ch, Pallavi, C. Padma, R. Kiran Kumar, T. Suguna, and C. Nalini. 2025. “Design of a 64-Bit SQRT-CSLA With Reduced Area and High-Speed Applications in Low Power VLSI Circuits”. Journal of VLSI Circuits and Systems 7 (1):40-45. https://doi.org/10.31838/jvcs/07.01.06.