BRAHMAIAH BATTULA, PUTTA VIJAYA LAKSHMI, SANDINENI LAKSHMI NAVYA SRI, SUNANDA KARPURAPU, and SIKHAKOLLI DURGA SRI SRAVYA. 2021. “Design a Low Power and High-Speed Parity Checker Using Exclusive–or Gates”. Journal of VLSI Circuits and Systems 3 (2):48-53. https://doi.org/10.31838/jvcs/03.02.06.