KOTHA GAYATHRI DEVI, KOTTAPALLI TEJASREE, MERUGUMALA KEZIA SWARNA SRI, and MOPIDEVI PRAVALLIKA. “Energy Reduction of D-Flipflop Using 130nm CMOS Technology”. Journal of VLSI Circuits and Systems, vol. 3, no. 2, Oct. 2021, pp. 34-41, doi:10.31838/jvcs/03.02.04.