BRAHMAIAH BATTULA, PUTTA VIJAYA LAKSHMI, SANDINENI LAKSHMI NAVYA SRI, SUNANDA KARPURAPU, and SIKHAKOLLI DURGA SRI SRAVYA. “Design a Low Power and High-Speed Parity Checker Using Exclusive–or Gates”. Journal of VLSI Circuits and Systems, vol. 3, no. 2, Oct. 2021, pp. 48-53, doi:10.31838/jvcs/03.02.06.