ch, Pallavi, C. Padma, R. Kiran Kumar, T. Suguna, and C. Nalini. “Design of a 64-Bit SQRT-CSLA With Reduced Area and High-Speed Applications in Low Power VLSI Circuits”. Journal of VLSI Circuits and Systems 7, no. 1 (March 12, 2025): 40–45. Accessed April 3, 2025. https://vlsijournal.com/index.php/vlsi/article/view/112.