Supriya B K, Arunraja A, Bremiga Gopalan Gandhimathi, S Sheeba Rani, N Sudhakar Reddy, and Deepali Rani Sahoo. “DFT Aware Test Architecture for Communication ICs: ATPG- Based Fault Detection on Lower Technology Node”. Journal of VLSI Circuits and Systems 7, no. 1 (July 4, 2025): 106–117. Accessed July 6, 2025. https://vlsijournal.com/index.php/vlsi/article/view/187.