C, Pakkiraiah, and R.V.S. Satyanarayana. “Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications”. Journal of VLSI Circuits and Systems 6, no. 1 (December 6, 2023): 7–18. Accessed November 23, 2024. https://vlsijournal.com/index.php/vlsi/article/view/51.