BRAHMAIAH BATTULA, PUTTA VIJAYA LAKSHMI, SANDINENI LAKSHMI NAVYA SRI, SUNANDA KARPURAPU, SIKHAKOLLI DURGA SRI SRAVYA. Design a Low Power and High-Speed Parity Checker using Exclusive–or Gates. Journal of VLSI Circuits and Systems [Internet]. 2021 Oct. 5 [cited 2024 Dec. 22];3(2):48-53. Available from: https://vlsijournal.com/index.php/vlsi/article/view/34