Vallabhuni Vijay, Chandra S. Pittala, K. C. Koteshwaramma, A. Sadulla Shaik, Kancharapu Chaitanya, Shiva G. Birru, Soma R. Medapalli, Varun R. Thoranala. Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits. JVCS [Internet]. 2022 Mar. 10 [cited 2024 Jul. 4];4(01):20-6. Available from: https://vlsijournal.com/index.php/vlsi/article/view/39