C P, R.V.S. Satyanarayana. Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications. Journal of VLSI Circuits and Systems [Internet]. 2023 Dec. 6 [cited 2024 Nov. 23];6(1):7-18. Available from: https://vlsijournal.com/index.php/vlsi/article/view/51