Journal of VLSI Circuits and Systems

Unified Multimodal 64-Bit Arithmetic Logic Unit for High-Performance Computing Architectures

2025-10-06T20:13:33+03:00

An Arithmetic Logic Unit (ALU) is the core component for any processing unit to perform arithmetical and logical operations for modern computing. The design for ALUs for specific tasks including integer and floating-point arithmetic, logical operations, data movement, and control functions influences the CPU architecture and digital system design. This work presents a unified ALU implemented in Verilog hardware description language (HDL), capable of performing arithmetic and logic operations across diverse numerical representations. The ALU is engineered to integrate logic unit, signed arithmetic processor, unsigned arithmetic processor, and floating-point arithmetic processor. The selection of operation is governed by select line signals to facilitate versatile user-driven functionality at the hardware level. To enhance the computational efficiency for handling multiplication of 64-bit signed and unsigned operands which generates 128-bit result, the proposed ALU architecture employs parallelism by processing the most significant and least significant bits simultaneously. A flexible mechanism for selective output enables the user to extract the desired segment of the result. Consolidating floating-point and fixed-point computations within a single ALU instance, the proposed architecture reduces the silicon area with reduced power dissipation and computational latency while streamlining routing complexities. This multi-modal ALU design with high-throughput is particularly suited for deployment in heterogeneous computing environments such as general-purpose processors, cryptographic accelerators, and machine intelligence hardware, where the rapid processing of heterogeneous data types is essential for workload optimization and energy-efficient system operation.

VLSI Circuits–Oriented Gate-Length-Dependent DC–RF Compact Modeling of AlInN/AlN/GaN MISHEMTs with SSEC Extraction

2025-12-22T12:52:52+03:00

This work develops a compact analytical DC-RF model based on VLSI-circuit design that accounts for gate-length scaling impacts in RF circuit designs using . In order to effectively simulate the drain current density, transconductance and the gate charge for use in simulating RF and microwaves circuits using technology, a two-dimensional electron gas (2-D) sheet-charge based formulation has been developed to account for flat-band voltage and polarization charge impacts. This model was validated with both TCAD simulations and experimental data for a range of gate lengths (from 0.1 to 0.3 μm), resulting in a maximum drain current density of 2.35 A/mm and an estimated cut of frequency of125 GHz when the gate length was 0.1 μm. In addition, a refined small-signal equivalent circuit (SSEC) extraction methodology, integrating conventional and gradient-based optimization techniques, is introduced to improve parasitic de-embedding accuracy. Extracted S-parameters enable robust frequency-domain characterization, yielding f_T=170 GHz and f_max=183 GHz. The proposed compact model demonstrates scalable, bias-consistent DC and RF prediction, making it well suited for VLSI RF and microwave circuit design and simulation using GaN MISHEMT technologies.

AI-Optimized Low-Power VLSI Solutions for Implantable Biomedical Devices Integrating Neural Networks and Bio-Signal DSP

2025-12-16T07:46:13+03:00

Biomedical devices that are implantable are increasingly based on on-chip intelligence and low-power computing as well as secure processing of physiological signals to facilitate continuous monitoring and closed-loop intervention. Conventional VLSI design systems are unable to satisfy the high power, latency, and reliability requirements of any long-term implantable system, particularly with neural-network inference and bio-signal DSP pipelines becoming the new norm with next-generation medical implants. The following paper describes an AI-based low-power VLSI design system with neural inference engines, real time physiological DSP, and adaptive power optimization designed specifically to be used in implantable systems. To reduce dynamic switching energy, optimise arithmetic precision and speed up convolutional bio-signal processing, machine learning is incorporated throughout the design process. An optimization framework with multiple objectives is used in order to meet the biomedical requirements of thermal safety, battery life, and energy restrictions that are biocompatible. The physics of simulation with 65 nm and 28 nm low-leakage CMOS nodes show that they can significantly reduce energy usage, increase the level of classification of neural and ECG signals, and become more resistant to signal artefacts. The suggested architecture proves to be highly suitable in pacemakers, neural prosthetics, wearable-implant hybrids and intelligent drug-delivery implantable devices that need continuous low-power AI-supported functionality. The work sets a common ground towards the combination of neural inference, DSP, and biomedical safety aspects to the next-generation implantable VLSI platforms.

Machine Learning-Assisted Automated VLSI Design for Bioinformatics Hardware Accelerators with Embedded Cryptographic Security

2025-12-16T07:54:57+03:00

The growing need of high-throughput bioinformatics computation, and the strict data privacy demands has further triggered the need to have hardware accelerators with both sophisticated processing and in-built cryptographic protection. The given paper introduces a machine learning-aided automated VLSI design system that should be used to create next-generation bioinformatics accelerators with embedded security primitives. The suggested approach capitalizes on the design-space exploration based on the learning approach, adaptive hardware synthesis, and on-board encryption to facilitate genomic alignment, protein structure modelling, and multi-omics signal analysis. Reinforcement learning and trained prediction models are auto-generate architectural choices which can be used to optimize datapaths, memory subsystems, and cryptographic blocks. Lightweight AES, hash and PUF authentication units embedded are used to guarantee confidentiality and integrity in biomedical processes where compliance with regulation is paramount. The given framework would be beneficial to both the edge and cloud-connected biomedical system because it allows increasing design scalability and decreasing the amount of manual engineering overhead. The experimental tests show that it is more efficient in design, has less power consumption, and is more efficient in computational throughput than traditional VLSI techniques. This is further enhanced by the fact that the ML-directed optimization further minimises development cycles, and guarantees security-performance balance of various bioinformatics kernels. This work introduces a single design paradigm, which is a unification of automated VLSI synthesis, machine intelligence, and cryptographic protection of secure biomedical hardware acceleration.

Privacy-Preserving Access Control for IoT Smart Homes Using Hyperledger Fabric Consortium Blockchain and Edge Computing on Raspberry Pi

2025-12-16T08:04:22+03:00

The problem of privacy and security continues to be a challenge in smart home Internet of Things (IoT) environments, in which heterogeneous devices share sensitive information and execute autonomous behaviours. The paper offers a privacy-protecting access control architecture implemented using hardware acceleration (Raspberry Pi gateway) by means of Hyperledger Fabric consortium blockchain and a VLSI-based edge security unit implemented on a Raspberry Pi gateway. The proposed co-design, unlike the traditional cloud-based authentication, includes the low-power cryptographic accelerator, a secure identity engine designed in Physical Unclonable Function (PUF) and a hardware access-control pipeline synthesized with the 65 nm CMOS technology. These hardware components enhance blockchain-intensive functions such as SHA-256 hashing, AES-GCM encryption, certificate verification, and policy analysis and minimise processing overhead that is commonly linked to blockchain-based IoT systems. The Hyperledger Fabric offers tamper-evident, decentralized access registration, and Raspberry Pi links with the custom accelerator through a hybrid software-hardware software flow of execution. Experimental testing shows that it has lower authentication latency, throughput efficiency and energy consumption compared to pure software-based blockchain validation. The hardware accelerator has a maximum of 61% lessening in transaction validation jolt and 47 percent power decrease when cryptographic tasks are performed. It improves privacy in that both the identity of the user, the control commands and the records of authorization are stored and authenticated using hardware bound cryptographic primitives and a distributed register. Hardware acceleration, blockchain consensus, and edge intelligence can ensure a high-quality solution to smart home access control, which is scalable.

AI/ML-Driven Electronic Design Automation Framework for Quantum-Aware VLSI Circuit Synthesis and Optimization in High-Performance Computing Applications

2025-12-15T12:29:24+03:00

Increased development of high-performance computing (HPC) has increased the pressure on new paradigms in VLSI circuit design, as device scaling is approaching scaling limits where quantum effects become important. Conventional electronic design automation (EDA) processes have difficulties in dealing with nonlinear interactions that occur when quantum tunnelling, leakage currents, and probabilistic switching are also present in the deeply scaled technology. To overcome them, this paper suggests an all-encompassing AI/ML-based EDA architecture, which incorporates quantum-aware modelling, predictive synthesis, and adaptive optimization of future HPC-oriented next-generation VLSI systems. The framework has incorporated machine learning-based parametric estimation, reinforcement learning on layout exploration and physics-guided neural models: non-classical effects in nanoscale transistors. Furthermore, the system uses generative learning algorithms to create multi-objective design trade-offs in terms of timing, power, area and quantum reliability. The hybrid digital-quantum design flow is presented, allowing to easily interchange the classical EDA operations and quantum-inspired device tests. Nanometer-scale benchmark circuit confirmation the efficiency of synthesis, accuracy of leakage prediction and rate of convergence of optimization are shown to be much enhanced with respect to more traditional EDA pipelines. The given methodology puts the emphasis on the role of intelligent automation as the means of guiding the VLSI research towards the point of quantum-awareness as the key to ensuring reliability, scalability, and energy efficiency in an HPC system.

Energy-Efficient Neural Network Accelerator Design for Real-Time DSP and Cryptographic Processing Using Advanced VLSI Architectures

2025-12-16T07:27:33+03:00

The development of artificial intelligence, real-time digital signal processing (DSP) and cryptographic workloads have been fueling the need to have highly efficient neural network accelerators embedded within state-of-the-art VLSI architectures. Traditional accelerators that are optimised to either DSP or cryptography are no longer capable of supporting the power, latency, and throughput requirements of the current embedded and high-performance computing systems. With the increasing complexity of neural workloads and the increasing security assurances needed with cryptographic operations, energy efficiency is becoming more important than ever. It is a unified, energy efficient accelerator design which combines the use of neural processing, DSP kernels, and cryptographic primitives, in a single VLSI system. The framework suggested utilizes hardware-aware quantization, systolic TA, reconfigurable DSP pipeline, and low-power cryptographic cores designed with the aid of machine learning-driven design frameworks. Learning is performed to search through architectural designs via reinforcement learning, and the single-objective bi-objective-optimization is directed by hardware-aware optimization of performance in terms of area, power and latency. Improved throughput-per-watt, low-latency processing and secure execution is experimentally proven using 7 nm and 5 nm design nodes compared to current accelerator designs. The findings indicate that the suggested architecture can be effectively applied to AI-based embedded systems, secure IoT systems, and real time edge intelligence that requires co-location of DSP and cryptographic operation. This paper adds a scalable energy aware VLSI accelerator design that can address the increased computational and security requirements of the next generation intelligent systems.

AI-Optimized Design Automation and Quantum-Inspired Secure VLSI Architectures for Edge and Autonomous Computing

2025-12-17T12:57:12+03:00

The high rate of growth of edge systems and autonomous systems requires real-time optimised, energy efficient and secure hardware architectures. The conventional VLSI design flows cannot accommodate such requirements because design complexity is on the rise, security threats are increasing, and also, high performance computing has to be done under stringent power limitations. A unified system of AI-based design automation, quantum-inspired logic optimization, and hardware security co-design of next-generation VLSI systems is described in this paper. The suggested approach allows the study of design space faster, increases the security level, and minimises power and delay, as well as, optimises the workload performance of edge and autonomous applications. The experiments show that there is a considerable improvement in the PPA (Power, Performance, Area), attack resistance and inference efficiency. The methodology is close to the current tendencies of VLSI and moves towards real-life applicability of secure and optimised architectures towards embedded intelligence.

Implementation of an Efficient RISC-V Processor Featuring a Novel Gshare Branch Prediction Technique

2025-11-18T12:32:23+03:00

RISC-V, characterized by its straightforward and open-source instruction set design, is becoming a compelling platform for contemporary IoT devices. Dynamic branch prediction, especially two-level methods and history/address hashing approaches such as Gshare, has demonstrated significant efficacy in alleviating control hazards in pipelined processors. This study introduces a 5-stage (IF–ID–EX–MEM–WB) RISC-V core that incorporates a Branch Prediction Unit (BPU), which merges a Branch Target Buffer (BTB) and a Pattern History Table (PHT) featuring 256 entries with 2-bit saturating counters. The PHT index is derived from XOR(GHR, PC[9:2]), while the BTB is refreshed utilizing the lower 8 bits of the PC. The design was executed from RTL to GDSII with Cadence Genus, Conformal, and Innovus on GPDK045 (45 nm) technology, illustrating feasibility beyond research confined to RTL or FPGA, such as RVCoreP. RTL simulation verified the accurate execution of all 37 RV32I instructions and attained roughly 90.4% accuracy in branch prediction for branch-intensive tasks. Post-layout results indicate that the design attained the target frequency (exceeding 50 megahertz), with a recorded maximum frequency of roughly 75 MHz. The overall power consumption of the core is around 15.078 mW across an area of roughly 0.69 mm², resulting in a core density of nearly 70 percent. These data validate the feasibility of employing two-level branch prediction in lightweight RISC-V microcontrollers.

Quantum-Inspired VLSI Architectures for Secure Cryptographic Signal Processing in Next-Generation AI-enabled hardware systems

2025-12-16T07:37:48+03:00

The sudden advent of AI-driven platforms and smart cyber-physical systems have rendered more and more demands on hardware frameworks that are capable of delivering quantum-inspired processing, secure cryptographic processing, and efficient signal-processing aptitudes all at once. The conventional VLSI architectures are constrained by the deterministic logic models which do not reflect the probabilistic characteristic of the quantum-inspired algorithms and the advanced cryptographic models. In order to fill this gap, this work introduces a single quantum-inspired VLSI that is optimised to implement secure signal processing in AI hardware of the next generation. The suggested system will combine approximate probabilistic computing blocks, reversible-logic embedded datapaths, and lightweight quantum-state emulation units to aid in increasing security, decreasing power usage, supporting parallel cryptographic transformations. The optimization methods based on machine learning are applied to explore architectures, allowing reconfiguration of cryptographic workloads and neural inference workloads and signal-processing workloads dynamically. The use of 5 nm and 7 nm technology nodes leads to simulation studies which show great improvement in throughput-per-watt, encryption latency and resistance to side-channel vulnerabilities. The architecture also minimises signal-processing overhead and signification of cryptographic diffusion properties which are important to edge AI deployments. The given work provides an addition of a scaleable quantum-inspired design model that can bridge the gap between traditional VLSI and new post-quantum computing requirements, and provide secure, energy-efficient, AI-operated hardware systems that can support defense, autonomous infrastructures, and future Internet of Things.