https://vlsijournal.com/index.php/vlsi/issue/feed Journal of VLSI circuits and systems 2024-06-28T17:27:00+03:00 Dr.M.Kavitha info@sccts.org Open Journal Systems <p><strong>Journal of VLSI circuits and systems (ISSN; 2582-1458)</strong> is open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design &amp; Circuits. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Circuits concepts and establishing new collaborations in these areas.</p> <div class="book_frg"><strong>Frequency: </strong>Half-Yearly (2019-2023)</div> <div class="book_frg"> Quarterly (2024 onwards)</div> <p><strong>Focus and Scope (not limited to):</strong></p> <ul> <li>Algorithms for VLSI Design Automation</li> <li>Advanced Computer Architecture</li> <li>Advanced CPLD Based Design</li> <li>Advanced FPGA Based Design</li> <li>Analog VLSI Design</li> <li>Analog&amp; Digital IC Design</li> <li>Asynchronous System Design</li> <li>Advanced Digital Design</li> <li>Analysis and Design of Digital Systems using VHDL</li> <li>Advanced Computer Architecture</li> <li>Advanced Computational Methods</li> <li>Computational Methods for VLSI</li> <li>CMOS RF Circuit Design</li> <li>Computer Aided VLSI Design</li> <li>Cryptology and Crypto Chip Design</li> <li>Digital System Design</li> <li>Digital Signal Processing Structures for VLSI</li> <li>Digital Image Processing for VLSI</li> <li>Data Structure &amp; Algorithm Analysis</li> <li>Design of VLSI System</li> <li>Digital Logic with Verilog</li> <li>Embedded Systems: High-Level Synthesis for VLSI Systems</li> <li>Electronic Design Automation Tools</li> <li>Electronic Packaging</li> <li>Functional and Formal Verification</li> <li>HDL Modelling</li> <li>Hardware-Software Co-design</li> <li>HDL Languages used for VLSI: Verilog &amp; VHDL</li> <li>Low Power VLSI Design</li> <li>Modelling and Synthesis with Verilog HDLMOS Circuit Design</li> <li>Mixed - Signal Circuit Design</li> <li>MEMS and IC Integration</li> <li>Nano Technology</li> <li>PCB Designing</li> <li>Process, Devices &amp; Circuit Simulation</li> <li>RF &amp; Bio MEMS</li> <li>Thermal Design of Electronic Equipment</li> <li>Solid State Electronics Devices</li> <li>System on Programmable Chip Design</li> <li>Simulation, Synthesis &amp; Verification of Integrated Circuits and Systems</li> <li>VLSI System Testing</li> <li>VLSI Process Technology</li> <li>VLSI Test &amp; Testability</li> <li>VLSI Architectures, Algorithms, Methods &amp; Tools for Modelling</li> </ul> https://vlsijournal.com/index.php/vlsi/article/view/110 Development of Synthesizable Filter-Centric Loop Filter Design for ADPLL Architecture in SoC 2024-06-28T17:14:04+03:00 Ravikumar G ravikumarg1308@gmail.com Venkatareddy D dvenkatreddy_ece@mgit.ac.in Asharani M ashajntu1@jntuh.ac.in <p>The emergence of all-digital phase-locked loop (ADPLL) filters marks a major advancement in the field of signal processing technology. These filters are engineered to align the phase and frequency of digital signals, ensuring accurate timing and accuracy in a wide range of applications. By using a digitally controlled oscillator (DCO) to adjust the frequency and compare it to a reference signal, ADPLL filters minimize phase differences, improve filtering efficiency, and reduce noise in digital communication systems. Due to their ability to adapt to different input signals and environmental factors, these filters are critical to modern electronic devices, especially in challenging applications such as wireless communications, data transmission, and clock synchronization. In this research work, the variable reset random walk filter is designed in ADPLL architecture. The complete ADPLL design is developed using Verilog HDL language and realized in Zynq 7000 all programmable SoC device. The resource and power utilization reports are compared with the existing ADPLL design. In other hands the Pk-to-Pk jitter and phase errors are compared, in all cases the proposed ADPLL design exhibits better performance compared to exiting ADPLL design.</p> 2024-06-28T00:00:00+03:00 Copyright (c) 2024 https://vlsijournal.com/index.php/vlsi/article/view/111 Development of Low Power GNSS correlator in Zynq SoC for GPS and GLONSS 2024-06-28T17:22:46+03:00 Arunalatha Botla gangarapulatha@gmail.com Kanaka Durga G scctssociety@gmail.com Chandrasekhar Paidimarry scctssociety@gmail.com <p>A low-power Global Navigation Satellite System (GNSS) correlator for GPS and GLONASS signals was developed using the Zynq System on Chip (SoC) technology. The main goal of this research was to create an efficient correlator that consumes minimal power while maintaining excellent signal processing capabilities. The proposed correlator architecture leverages the programmable logic and processing capabilities of the Zynq SoC, employing a combination of hardware and software implementations to achieve maximum power efficiency.The design of the GNSS correlator is implemented using Verilog, and the Verilog code is realized on the Zynq SoC device. To assess the resource utilization and power consumption of the proposed design, the Xilinx Vivado IDE is utilized for resource estimation and power analysis. Simulation results demonstrate the high precision of the low-power GNSS correlator in processing GPS and GLONASS signals.The findings of the study indicate significant power savings compared to conventional correlator designs. The proposed design enhances power utilization without compromising signal processing capabilities by utilizing optimizing the correlator architecture. The development of a low-power GNSS correlator facilitates the advancement of energy-efficient GNSS receiver designs, particularly for applications with limited power resources. The proposed architecture not only extends battery life but also simplifies the integration of GNSS positioning capabilities into devices with restricted power availability.</p> 2024-06-28T00:00:00+03:00 Copyright (c) 2024