Journal of VLSI Circuits and Systems

Impact of Digital Technologies on Economic and Marketing Innovation and Competitiveness within VLSI System Employment

2024-11-12T22:15:08+03:00

This article examines the role of digital technologies in shaping economic and marketing innovation and competitiveness for firms engaged in employment in Very Large Scale Integration (VLSI) systems. The evolution of semiconductor technology has made
integrating digital technologies a critical part of innovation in VLSI design, production, and application. The study begins by exploring the current state of play in VLSI technology and the role of digitalization in enhancing operational efficiencies and fostering innovative
approaches to product development. An extensive analysis of recent developments in VLSI systems employment demonstrates how digital technologies such as artificial intelligence (AI), machine learning, and automation can facilitate improved design optimization, yield enhancement, and reduce time-to-market for semiconductor products. The enhanced design efficiencies and timely product development accruing from applying digital technologies translate into a greater competitive advantage for firms in a global marketplace. The article examines the synergies between digital technologies and economic innovation. It highlights how firms can leverage digital technologies to enhance data analytics and advanced manufacturing processes, creating more intelligent and capable VLSI systems for next-generation electronics, telecommunications, consumer goods, and many other applications. The article concludes by contending that embracing digital technologies is necessary and critical for economic innovation and competitiveness for firms engaged in VLSI systems employment. The article also calls for further examination of emerging digital tools and platforms to shape the semiconductor industry’s trajectory at a much faster pace, leading to more robust economic growth and technological advancement.

Design and Optimization of Coarse-Grained Reconfigurable Array (CGRA) Architecture for Efficient Processing-in-Memory (PIM) Systems

2024-11-14T14:18:16+03:00

The Coarse-Grained Reconfigurable Array (CGRA) architecture for Efficient Processing-in-Memory (PIM) systems is presented in this article. PIM architectures that incorporate computational capabilities directly into memory present a promising solution to mitigate the memory wall issue. There are several difficulties in CGRA architecture optimization for PIM systems especially when it comes to striking a balance between area efficiency, power consumption and performance. The proposed framework tackles these problems by examining crucial design components like processing element (PE) architecture memory hierarchy integration and interconnect design. Using a design space exploration (DSE) methodology we assess various CGRA configurations to find the optimal trade-offs between computation throughput, power consumption and silicon area utilization. To assist in selecting effective architectures that meet different application workloads the framework combines performance analysis and advanced modeling techniques. Based on test results, the optimized CGRA architecture for PIM achieves significant improvements in processing performance (20 percent increase in throughput), area reduction and energy efficiency (up to 40 percent reduction in power consumption) when compared to conventional PIM designs. Our architecture is well-suited for data-intensive applications such as machine learning and graph analytics since these enhancements are achieved without compromising computational accuracy or scalability.

Adaptive VLSI Design Using Dynamic Voltage and Frequency Scaling (DVFS) for Low-Latency IoT Communication Networks

2024-11-14T14:51:45+03:00

The best and most compatible hardware solutions need to be developed to meet the growing demand for communication in Internet of Things (IoT) networks. This paper suggests using dynamic voltage and frequency scaling or DVFS for designing adaptive VLSI circuits for small IoT communication networks. DVFS is used to adjust the operating voltage and frequency of circuits and reduce power consumption when network traffic is light. It also maintains high-speed operation under heavy loads. By satisfying the requirements of the oscillating network the proposed VLSI design preserves low latency and high power efficiency. Simulations and prototype implementations show that in comparison to conventional VLSI designs the system features notable improvements in both communication speed and power consumption. These findings show that by strengthening power and traffic performance in IoT networks through the integration of VLSI circuits DVFS can be a good option for resource-constrained IoT devices and real-time applications.

Design of a optimized CMOS Differential Amplifier using Craziness-based PSO

2025-01-29T10:29:23+03:00

Particle swarm optimization (PSO) is acomputational method used for solving different types of optimization problems. The social behaviors of fish schooling and flocks of birds mostly influence the PSO. PSO uses a collection of particles to explore the search space and locate the best possible solution.Each particle updates its position depending upon experience of itself or from neighboring particles, aiming to find the best solution in terms of the objective function being optimized.Crazinessbased Particle Swarm Optimization (CRPSO) is an advanced variation of the standard Particle Swarm Optimization (PSO) algorithm.CRPSO introduces a "craziness" factor to enhance the diversity of the swarm and prevent premature convergence to local optima.This paper deals with the design of a CMOS differential amplifier circuit with a current mirror load using CRPSO algorithm. The optimized sizes of the transistors are obtained using CRPSO to decrease the overall transistor area while meeting design limitations. The results achieved using the CRPSOare validated in the SPICE. The simulation result shows the superiority of CRPSO in the design of differential amplifier.

Efficient Design of Up Sampler and Down Sampler using Single Electron Transistor-Metal Oxide Semiconductor Field Effect Transistor

2025-01-19T15:03:50+03:00

The increasing demand for high performance and low power, energy efficient electronics has led to significant advancements in nanoscale devices. Among these the single electron transistor (SET) stands out due to its potential for ultra low power consumption and high sensitivity. This article presents an in depth study on the efficient design of SET based up samplers and down samplers. These components are crucial in modern communication systems for converting signals between different sampling rates. Our findings indicate that SETs offer substantial potential for reducing power consumption and enhancing the precision of sampling rate conversions although challenges such as thermal stability and integration with existing systems remain. This study aims to contribute to the development of more efficient and compact communication technologies by leveraging the unique properties of SETs.

Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits

2025-02-28T10:59:33+03:00

The main areas of research in VLSI system design include area, high speed, and power-efficient data route logic systems. The amount of time needed to send a carry through the adder limits the pace at which addition can occur in digital adders. One of the quickest adders, the Carry Select Adder (CSLA), is utilized by various data processing processors to carry out quick arithmetic operations. It is evident from the CSLA's structure that there is room to cut back on both the area and the delay. This work employs a straightforward and effective gate-level adjustment (in a regular structure) that significantly lowers the CSLA's area and delay. In light of this adjustment Square-Root Carry Select Adder (SQRT CSLA) designs with bit lengths of 8, 16, 32, and 64. When compared to the standard SQRT CSLA, the suggested design significantly reduces both area and latency. Xilinx ISE tool is used for Simulation and synthesis. The performance of the recommended designs in terms of delay is estimated in this study using the standard designs. The study of the findings indicates that the suggested CSLA structure outperforms the standard SQRT CSLA.

Automated Compliance Systems in International Trade: The Role of AI and VLSI Systems in Streamlining Customs Procedures

2025-03-18T13:27:47+03:00

In an increasingly globalized economy, the efficiency of international trade is paramount, and customs procedures play a critical role in facilitating the smooth flow of goods across borders. This article explores the integration of Automated Compliance Systems (ACS) in international trade, focusing on the transformative impact of Artificial Intelligence (AI) and Very Large Scale Integration (VLSI) systems. We examine how these technologies can streamline customs procedures by enhancing data processing capabilities, improving accuracy in compliance checks, and reducing processing times. Through a comprehensive analysis of current practices, we highlight the potential of AI-driven algorithms to predict and mitigate compliance risks, while VLSI systems enable the rapid processing of vast amounts of data. The findings suggest that the adoption of ACS powered by AI and VLSI not only enhances operational efficiency but also fosters greater transparency and security in international trade. This article seeks to offer valuable perspectives regarding the future of automated compliance within the dynamic and rapidly changing landscape of international trade.

High Speed Energy Efficient Latch Architectures for Sequential Circuit Design

2025-02-12T11:05:41+03:00

As per the escalating demand for portable and battery-powered electronic devices, the requirement of energy-efficient, high-speed devices with minimal area has become increasingly imperative in this era of sustainable electronics and green computing. Latches serve as fundamental elements essential for the operation of sequential circuits in Internet of Things (IoT), Edge computing, and high-performance processors. The bulk of on-chip elements in a processor is often composed of sequential parts such as memory, registers, counters and flip-flops, wherein the foundational component is a data latch. This research paper puts forward two level sensitive latch energy- efficient designs using 6 transistors and 5 transistors respectively. The proposed designs are assessed under multiple supply voltages and temperatures. Additionally, corner analysis and Monte Carlo analysis are conducted on the proposed latch designs to validate their robustness and stability, ensuring their sustainability and ability to withstand high error rate at different operating conditions. The results confirm reduced energy consumption, delay and output noise with improved performance of the latches with an improvement of PDP by 10 folds and the delay is reduced by a factor of 10-2 with an area occupancy of 5.6024 µm2 and 4.7183 µm2 for the two proposed designs. Also, a 3-bit shift register is designed with the proposed design to demonstrate the successful application of these designs.

Efficient VLSI Architecture Integrating Vedic Mathematics for Square Computation

2024-12-08T20:51:01+03:00

Implementation of combinational logic circuits in combination with Vedic maths sutra has many advantages over traditional multiplier circuits, such as reduced time delay, less resource utilization, and less power consumption by the selection of the proper FPGA family. Multiplication is one of the important instructions used for performing complex operations in DSP processors. The proposed paper presents the use of Urdhva-Tiryagbhyam Sutra for the square operation. The results of the designed Vedic circuit show that, there is a 17.36% reduction in time delay and an 8.13% reduction in power consumption in Spartan-7 than Artix-7. There is a 33.6% reduced time delay than the Nikhilam sutra, 45.87% reduced delay than the Yavadunam sutra, 87.07% less delay than the Booth multiplier, and 67.83% reduced delay than Booth Wallace multiplier. Thus, implementing the Vedic Sutra for finding the square of a given number causes a reduction in time delay, power consumption and small chip size.

A 3.7-4.8GHz Programmable Integer-N PLL With Multi-Modulus Divider and Tunable VCO in Standard 45nm CMOS Technology

2025-03-04T11:06:40+03:00

This paper presents a comprehensive study of each phase-locked loop (PLL) component to enhance its flexibility for various applications. First, a differential voltage-controlled oscillator (VCO) is designed with programmability enabled through a capacitor bank controlled by a 4-bit word, allowing it to cover a wide frequency range. Second, an integer- type frequency divider is implemented using a multi-modulus technique, introducing programmability to the divider. The multi-modulus divider consists of seven divider stages, where each stage can divide the input frequency by a factor of two or three, controlled by a seven-bit control word, enabling a wide range of division values. Since the frequency decreases after each stage, each divider stage is optimized for power efficiency. Third, a phase-frequency detector is designed with an extended phase detection range from

-2π to +2π. Additionally, a charge pump and loop filter are designed to provide a stable control voltage, ensuring the VCO operates at the desired frequency. The PLL is designed using the Cadence Virtuoso Analog Design Environment with 45nm CMOS technology and simulated using the Spectre simulator. Operating at a 1.1V supply, the PLL achieves a lock state in 14μs while consuming 27.4mW of power. The designed PLL delivers stable output frequencies in the range of 3.7–4.8GHz. The PLL shows PSRR of about 8dB when a small AC noise source (Vn=1mV) applied on the power supply.

VLSI Systems as the Engine for the Knowledge Society: Enabling Information Culture through Technological Innovation

2025-05-30T14:03:35+03:00

The emergence of the knowledge society and the pervasive nature of information culture are inextricably linked to advancements in digital technologies, fundamentally enabled by Very Large Scale Integration (VLSI) circuits and systems. This paper explores the critical role of VLSI innovation in powering the infrastructure required for generating, processing, storing, and disseminating vast amounts of information. We examine how the increasing demands for computational power, energy efficiency, high-speed connectivity, and robust security, driven by societal trends, translate into specific challenges and opportunities for VLSI design. The study analyzes how various VLSI architectures, including multicore processors, GPUs, FPGAs, and ASICs tailored for AI, facilitate the core functions of the knowledge economy. Furthermore, it investigates how VLSI design paradigms are shifting to address issues like information overload and the digital divide from a hardware perspective. We explore the symbiotic relationship where VLSI advancements enable new information practices, while the needs of the information culture steer the trajectory of VLSI research and development, particularly in areas like low-power design, hardware security primitives, and specialized accelerators. Drawing upon existing models of societal change and identifying key VLSI technological drivers, this work proposes a conceptual framework highlighting the co-evolution of VLSI systems and the informationcentric society. The implications suggest that continued innovation in VLSI, focusing on performance, efficiency, and security, is paramount for the sustainable development of the global knowledge society.

Energy-Efficient GNRFET-Based Ternary Full Adder for Next-Generation Integrated Circuits

2025-04-21T14:06:58+03:00

Ternary logic is an appealing alternative to binary logic, because it reduces circuit complexity, implementation area, and power consumption. This paper covers Graphene Nanoribbon Field Effect Transistor (GNRFET) based Ternary Full Adder (TFA) used for Next Generation Integrated Circuits. Instead of utilizing two states, ternary logic uses three states to execute efficiently in computation and data processing. This significantly reduces the complexity of the arithmetic circuit, making it suitable for high-speed applications. New technology, based on GNRFET, proposed as possible successor to CMOS technology. Proposed TFA1 and TFA2 with 98 transistors and 68 transistors, simulated using the HSPICE Simulator with 32nm MOS-GNRFET Nano Hub Models. Simulated results reveal that the proposed TFA2 has reduced Power Delay Product (PDP) than the proposed TFA1 approach. The most essential parameter of digital circuit design used in Multi Valued Logic (MVL) is the threshold voltage of GNRFET, changed in ternary logic to reduce power consumption and delay. Low power consumption and fast processing of these circuits make it suitable for the next-generation integrated circuits