Journal of VLSI Circuits and Systems

Development of Synthesizable Filter-Centric Loop Filter Design for ADPLL Architecture in SoC

2024-06-28T17:14:04+03:00

The emergence of all-digital phase-locked loop (ADPLL) filters marks a major advancement in the field of signal processing technology. These filters are engineered to align the phase and frequency of digital signals, ensuring accurate timing and accuracy in a wide range of applications. By using a digitally controlled oscillator (DCO) to adjust the frequency and compare it to a reference signal, ADPLL filters minimize phase differences, improve filtering efficiency, and reduce noise in digital communication systems. Due to their ability to adapt to different input signals and environmental factors, these filters are critical to modern electronic devices, especially in challenging applications such as wireless communications, data transmission, and clock synchronization. In this research work, the variable reset random walk filter is designed in ADPLL architecture. The complete ADPLL design is developed using Verilog HDL language and realized in Zynq 7000 all programmable SoC device. The resource and power utilization reports are compared with the existing ADPLL design. In other hands the Pk-to-Pk jitter and phase errors are compared, in all cases the proposed ADPLL design exhibits better performance compared to exiting ADPLL design.

Development of Low Power GNSS correlator in Zynq SoC for GPS and GLONSS

2024-06-28T17:22:46+03:00

A low-power Global Navigation Satellite System (GNSS) correlator for GPS and GLONASS signals was developed using the Zynq System on Chip (SoC) technology. The main goal of this research was to create an efficient correlator that consumes minimal power while maintaining excellent signal processing capabilities. The proposed correlator architecture leverages the programmable logic and processing capabilities of the Zynq SoC, employing a combination of hardware and software implementations to achieve maximum power efficiency.The design of the GNSS correlator is implemented using Verilog, and the Verilog code is realized on the Zynq SoC device. To assess the resource utilization and power consumption of the proposed design, the Xilinx Vivado IDE is utilized for resource estimation and power analysis. Simulation results demonstrate the high precision of the low-power GNSS correlator in processing GPS and GLONASS signals.The findings of the study indicate significant power savings compared to conventional correlator designs. The proposed design enhances power utilization without compromising signal processing capabilities by utilizing optimizing the correlator architecture. The development of a low-power GNSS correlator facilitates the advancement of energy-efficient GNSS receiver designs, particularly for applications with limited power resources. The proposed architecture not only extends battery life but also simplifies the integration of GNSS positioning capabilities into devices with restricted power availability.

RoBA Multiplier-Driven FIR Filter Synthesis: Uniting Efficiency and Speed for Enhanced Digital Signal Processing

2024-07-02T11:35:44+03:00

Abstract —The main objective of this project includes, enhance the computational efficiency of DSP systems which make them operate more efficiently. Traditional DSP computations can be slow, so sometimes it's more important to be fast than completely accurate. To craft a Digital Signal Processor (DSP) systems even faster and save energy, researchers have designed circuits that approximate calculations, sacrificing a bit of precision. By this proposed solution, we designed a RoBA multiplier type for filters that rounds numbers to the closest whole number. By simplifying the multiplication process, this approximation reduces system’s size and speeds up the operation. Considering the fact that the multiplier typically functions at a slower pace compared to other components, this adjustment is anticipated to enhance the filter's overall efficiency. We compared the Vedic multiplier to the proposed ROBA multiplier. The acquired results showcase the power, area, number of slice LUTs, number of bonded Input/Output Buffers, and delay related to this multiplier and FIR filters were greatly decreased, while the multiplier speed increased proportionally.

Index Terms— Approximation multiplier, Energy-efficient computation, Accuracy trade-off, Performance evaluation, FIR filter, Multiplication strategies, Speed optimization.

A Novel Machine Learning Model for Early Detection of Advanced Persistent Threats Utilizing Semi-Synthetic Network Traffic Data

2024-08-07T04:48:19+03:00

Advanced Persistent Threats are not merely a buzzword, these highly sophisticated and stealthy cyber threats are characterized by their ability to infiltrate and persistently operate within target systems for extended periods, often remaining undetected until significant damage has been done. APTs have emerged as a formidable adversary, and it frequently attack important infrastructure, government entities, and private businesses. This research paper embarks on an examination of APTs, shedding light on their characteristics and strategies. The proposed model APTGuard in the paper presents vital way to detect and counter this menace effectively, employing a methodology that involves utilizing a Semi-Synthetic dataset using 6.8 Million samples of processed network flows for training and testing. Orchestrating four pivotal phases: data collection, feature selection, data pre-processing and applying of machine learning algorithms. Encompassing the application of the algorithms: long short-term memory (LSTM), logistic regression (LR), support vector machine (SVM), and k-nearest neighbours (KNN), with comparing the results, the paper emphasizes that APT Guard, achieves a notable accuracy of 99.89 % using 83 features. The paper makes a substantial contribution to create effective method for detecting and resist hidden and malicious APTs

Low Power System on Chip Implementation of Adaptive Intra Frame and Hierarchical Motion Estimation in H.265

2024-08-07T04:56:02+03:00

Over the years, video compression standards have evolved and helped distribute multimedia content with greater ease. H.265 or High Efficiency Video Coding (HEVC) is one of the best lossy video codecs released as successor to H264 which offers better compression. This analysis is focused on tackling the computation needs of H.265 encoding through System on Chip (SoC) based implementations. The SoC platform has both ARM and FPGA architectures to handle floating point and fixed-point operations with parallelism respectively. The intended methodology is implemented using adaptive intra-frame prediction and hierarchical motion estimation suitable for SoC implementation to bridge the current gap. The innovation of this approach is that the parallel processing capabilities built into SoCs are used to improve intra-frame prediction and motion estimation efficiency. This proposed method involves the adaptive mechanisms for intra-frame prediction as well as a hierarchical structure of motion estimation to balance computational load and resource consumption. In conventional intra prediction, all the 35 modes are implemented, and the best mode is selected based on the Sum of Absolute Difference (SAD) value. In SoC this process can be implemented in parallel by using non-blocking modules for all the 35 modes. In order to improve the efficiency further, edge detection and content analysis modules are added to analyse the blocks before the modes are selected. This make sures that only required modes are executed based on the content that is present in the block. The traditional motion estimation module is improved by adding a hierarchical framework to select the best matching block more effectively. To solve the power consumption problems, Intelligent Clock Gating (ICG) is applied in order to switch off idle modules and hence reduce dynamic power consumption drastically. This low-power optimization results in extended operation times for portable devices while minimizing thermal footprint. The proposed methodology successfully improved the overall efficiency of the H.265 framework.

Design of Novel High Speed Energy Efficient Robust 4:2 Compressor

2024-07-25T10:20:36+03:00

Multipliers are crucial in deciding the overall efficiency of the arithmetic circuits. Compressors are one of the vital components of the multipliers. This paper presents a new architecture for a 4:2 compressor, utilizing a novel truth table as well as internal equations. Additionally, the research investigates the methodology to incorporate a fast compressor into the XOR-XNOR circuit framework. Significantly, the suggested design has fewer transistors as compared to the existing 4:2 compressors. Four different and existing 4:2 compressors are examined closely for the comparative analysis with the proposed circuit. The suggested structure is compared with the latest ones found in modern publications, considering the power usage, latency as well as space optimization along with the Monte Carlo and Corner analysis. The proposed compressor has 49% lesser delay, 53% lower Power Delay Product and 76.27% lesser Energy Delay Product than the other prevailing compressor designs. Architecture simulation is performed using Cadence Virtuoso tool in 45 nanometer CMOS technology with power supply of 1 volt.

Transforming Economic Development through VLSI Technology in the Era of Digitalization

2024-11-12T22:00:43+03:00

This article highlights the significance of Very Large Scale Integration (VLSI) technology in the digital economy. VLSI technology has made noteworthy inroads into economic development. The article’s spatial contextualization explores the applications of VLSI technology in different economic sectors. The research scrutinizes the efficacy of using VLSI technology in terms of cost, new product development, operationalization, competitiveness, economies of scale, and time to market. The study also clarifies that the VLSI paradigm shift aligns with the digitalization of the economy. Aspirational industries such as health, telecommunications, and manufacturing are increasingly embracing the paradigm shift towards applying VLSI technology in implementing intelligent systems,
communication tools, and compliance devices, leading to enhanced economic growth. The analysis provides evidence-based examples of VLSI technology applications and achievements from other countries. The emphasis on contextualization during the study was paramount to help the reader grasp the significance of VLSI technology in the digital economy and assess the implications of extending its application in various critical sectors. Unveiling the regional initiatives undertaken by key sustainable development goals is geared towards developing robust partnerships that leverage VLSI technology for economic development. The context of the increasing transnational implementation of VLSI technology in various economic sectors necessitated a first-person narrative to aid the reader in understanding how and why VLSI technology has become critical in economic development. The study clarifies the strategies, approaches, and operationalization concerning VLSI technology, including its capabilities in streamlining operations, enhancing competitiveness, time to market, value innovations in health, and delivering efficiencies in manufacturing scenarios.

Reversible Vedic Direct Flag Divider in Key Generation of RSA Cryptography

2024-07-26T12:20:00+03:00

Reversible logic does not dissipate energy, and information loss never occurs. So, this futuristic technology is forced towards many applications involving less energy dissipation. This work targets the design of a new Vedic divider circuit and its implementation using reversible gates. The Direct Flag Vedic Division Method (DFVDM) is a new methodology, and it is addressed in this proposed work using reversible logic. We have utilized basic reversible gates in the block-level construction and shown that the proposed Reversible Direct Flag Vedic Division Method (RDFVDM) implementation has quantum parameter efficiency as well as area power and delay efficiency. This divider circuit inherits many advantages, such as fewer garbage outputs and a minimum quantum cost. Simulation investigations have been done by Cadence Tool. The proposed Vedic divider is also compared using reversible structural metrics like garbage outputs, constant inputs, and quantum cost with existing works, and the results showcase that RDFVDM excels over the equivalent designs. In terms of energy usage, RDFVDM outperforms by about 19%. Also, the 5% reduction is observed in Quantum Cost implementation compared to other state of art designs.

Design and Performance Analysis of Adiabatic Logic Circuits Using FinFET Technology

2024-11-12T23:03:34+03:00

Power dissipation is now a major concern in large-scale integration (VLSI) design, particularly in high-performance, low-power applications, as semiconductor technology shrinks. Because of its reputation for energy harvesting, adiabatic logic provides a practical means of reducing the dynamic power consumption of integrated circuits. Unlike conventional planar MOSFETs, FinFET technology offers better electrostatic control, lower losses, and greater scalability. This paper proposes the design and performance analysis of adiabatic logic circuits using FinFET technology. The study applies FinFET technology at 22 nm and 14 nm process nodes to implement important adiabatic logic families such as adiabatic positive feedback logic (PFAL) and energy recovery logic (ECRL). The circuits are designed in a simulated manner and their performance is evaluated in terms of latency, power efficiency, and power dissipation in a standard Cadence environment. To demonstrate the benefits of FinFET-based adiabatic designs to achieve lower power consumption, a comparative analysis with conventional CMOS circuits is also depicted. FinFET-based adiabatic circuits are especially well-suited for low-power VLSI systems, as demonstrated by the considerable reductions in power dissipation and energy per operation found in the simulation results.

Energy-Efficient High Speed Quantum-Dot Cellular Automata (QCA) based Reversible Full Adders for Low-Power Digital Computing Applications

2024-11-12T23:18:33+03:00

QCA is a promising nanotechnology that reduces transistor-based circuitry to provide notable speed and energy efficiency benefits. To further enhance performance and lower power consumption, QCA is integrated with reversible computing which is known to reduce power dissipation. This paper presents the design and analysis of high-speed, energy efficient reversible full adders using quantum dot cellular automata (QCA) technology for low-power digital computing applications. The goal of the proposed design is to create high-speed low-power full adders by optimizing reversible logic gates like the Fredkin, Toffoli and Peres gates. The design achieves notable reductions in power dissipation compared to traditional CMOS-based designs by utilizing the special ability of QCA
technology to operate with minimal switching energy. Today, creating complete stacking circuits that meet the growing demands is one of the biggest challenges to VLSI architects. The suggested QCA-based reversible full adders which can be used in emerging low-power high-speed digital applications like mobile computing cryptography and Internet of Things devices show improved performance in terms of energy efficiency,speed, latency, and fault tolerance through thorough simulation and analysis. According to experimental results, the new design provides improved integration and scalability for upcoming quantum-based architectures, opening the door for effective long-lasting digital systems.

VLSI-Based MED-MEC Architecture for Enhanced IoT Wireless Sensor Networks

2024-11-14T11:10:05+03:00

Large-scale integration and IoT wireless sensor network deployment are necessary for performance optimization and energy consumption reduction (VLSI). This paper presents the VLSI implementation of the Multi-Edge Motion Detection and Estimation (MED-MEC) algorithm for IoT WSN. Enhancing data processing capabilities and reducing power consumption are core components of the MED-MEC design which are critical to IoT device capabilities. VLSI design using FPGA platforms can handle the complexity of motion calculations an important task for many Internet of Things applications such as intelligent surveillance systems and environmental monitoring. Research results show that the MED-MEC architecture significantly reduces power consumption while maintaining fast accurate data. The projects modular structure allows for scalability and compatibility with other WSNs making it a flexible solution for future Internet of Things applications. Through the improvement of IoT WSN capabilities through VLSI technology more dependable and energy-efficient IoT applications can be realized as this study shows.

Implementation of VLSI Systems Incorporating Advanced Cryptography Model for FPGA-IoT Application

2024-11-14T11:44:10+03:00

This article presents the construction of VLSI systems, including a contemporary encryption technique, appropriate for FPGA-based Internet of Things applications. Modern encryption algorithms are directly incorporated into VLSI systems as part of the plan to improve data transmission security in Internet of Things networks while maintaining high efficiency and low energy consumption. Because so many things in our environment require unique addresses the Internet of Things (IOT) requires the use of the IPv6 protocol. Compared with the traditional method there is a discernible decrease in energy consumption and a discernible increase in processing speed. To compare the outcomes with existing encryption this work aims to develop a VLSI architecture that excels in high performance and resource efficiency. Real-world Internet of Things applications can benefit greatly from the proposed system which combines processing energy security and energy efficiency. The aforementioned findings indicate the possibility of fusing cutting-edge cryptography with VLSI designs to create practical secure and expandable solutions for the upcoming wave of Internet of Things systems.

VLSI architecture-based implementation of motion estimation algorithm for Underwater Robot Vision System

2024-11-18T10:10:24+03:00

Motion Estimation (ME) is a computationally intricate issue often affected by non-exact solutions. Consequently, it is imperative to embrace many methodologies and assumptions. Velocity is an essential variable for Underwater Robot Vision (URV) navigation, yet its
estimation poses significant challenges. Conventional techniques, such as the Global Positioning System (GPS), are ineffective underwater, while alternative approaches need to calculateocean current's velocity or employ sound sensors. Nonetheless, these systems possess inherent limits. A viable method to calculate the velocity of URVs is through the utilization of Computer Vision (CV) systems when a marine structure is inside the URVs field of view, as these sensors are not affected by the same issues as acoustic routing or the influence of ocean currents. This study devised an algorithm that estimates a vehicle's rotational velocity (RV) and axial velocity (AV) by utilizing the motion field derived from the optical ME technique. The algorithms were evaluated in simulated settings, and the findings were shown using several approaches for ME. The ME method was found to function as predicted, with a maximum error of 2.23% in the conducted tests, and showed greater robustness under challenging underwater situations. This work also presented a hardware Programmable Gate Arrays (FPGAs) to enable real-time computation of dense optical motion for Video Graphics Array (VGA) images, utilizing the ME method.