https://vlsijournal.com/index.php/vlsi <p>The <em>Journal of VLSI Circuits and Systems</em> is a peer-reviewed journal committed to publishing high-impact research in the field of Very-Large-Scale Integration (VLSI) design and systems engineering. The journal provides a platform for disseminating cutting-edge innovations that span the full spectrum of theoretical advances, simulation models, architecture design, physical implementations, and system-level integration in VLSI technology. (ISSN - 2582-1458)</p> <p>The journal invites original research papers, reviews, and application-driven studies that explore novel methodologies, tools, and trends across digital, analog, mixed-signal, and RF integrated circuits, as well as embedded and neuromorphic systems.</p> <p><strong>The journal covers a broad spectrum of topics related to VLSI circuits and systems, including but not limited to:</strong></p> <ol> <li><strong> VLSI Circuit Design</strong></li> </ol> <ul> <li>Low-power, high-speed digital circuit design methodologies.</li> <li>Analog and mixed-signal integrated circuits (ADC/DACs, PLLs, oscillators).</li> <li>Emerging logic families: adiabatic, quantum-dot cellular automata (QCA), reversible logic.</li> <li>Radiation-hardened and fault-tolerant circuit design.</li> <li>Clocking strategies, synchronization circuits, and time-interleaved designs.</li> </ul> <ol start="2"> <li><strong> Design Automation and EDA Tools</strong></li> </ol> <ul> <li>Hardware Description Languages (HDL), High-Level Synthesis (HLS), and Register Transfer Level (RTL) design.</li> <li>Placement, routing, and layout optimization.</li> <li>Logic and physical synthesis for power, performance, and area (PPA).</li> <li>AI/ML-driven EDA and design space exploration.</li> <li>Formal verification, equivalence checking, and constraint-driven simulation.</li> </ul> <ol start="3"> <li><strong> VLSI System Architectures</strong></li> </ol> <ul> <li>System-on-Chip (SoC), Network-on-Chip (NoC), and Chiplet-based modular architectures.</li> <li>Hardware/software co-design and hardware accelerators for edge and cloud computing.</li> <li>Memory subsystems: SRAM, DRAM, eNVM, MRAM, ReRAM integration.</li> <li>Application-specific architectures for AI, DSP, cryptography, and bioinformatics.</li> </ul> <ol start="4"> <li><strong> Emerging Trends and Technologies</strong></li> </ol> <ul> <li>3D ICs, Through-Silicon Vias (TSVs), and heterogeneous integration.</li> <li>Neuromorphic, brain-inspired, and spiking neural network hardware.</li> <li>Quantum VLSI circuits and cryo-CMOS design challenges.</li> <li>Photonic and plasmonic interconnects and optical VLSI.</li> <li>Approximate computing and in-memory computation (IMC).</li> </ul> <ol start="5"> <li><strong> Hardware Security and Reliability</strong></li> </ol> <ul> <li>Secure VLSI design, side-channel attack mitigation, and logic obfuscation.</li> <li>Hardware Trojans, counterfeit detection, and Physically Unclonable Functions (PUFs).</li> <li>Process variation analysis, aging-aware design, and reliability enhancement techniques.</li> <li>Design-for-testability (DFT), built-in self-test (BIST), and fault modeling.</li> </ul> <ol start="6"> <li><strong> AI and Reconfigurable VLSI Systems</strong></li> </ol> <ul> <li>FPGA/ASIC implementations of deep neural networks, transformers, and edge-AI.</li> <li>Real-time processing using dynamic partial reconfiguration.</li> <li>Hardware-aware neural architecture search (NAS) and pruning techniques.</li> <li>Custom tensor processors and systolic arrays for AI/ML inference and training.</li> </ul> <ol start="7"> <li><strong> Applications and Benchmarking</strong></li> </ol> <ul> <li>VLSI solutions for biomedical implants, autonomous vehicles, IoT, AR/VR, and robotics.</li> <li>Edge-computing accelerators with ultra-low power constraints.</li> <li>Energy-harvesting and battery-less VLSI systems.</li> <li>Benchmarking methodologies for performance, energy-efficiency, and silicon area.</li> </ul> <p>The journal targets academic researchers, VLSI designers, industry professionals, and students, aiming to advance VLSI circuit and system design through high-quality research.<br /><br /><strong>Frequency</strong> - 2 issue Per Year<br /><strong>ISSN</strong> - 2582-1458</p> SOCIETY FOR COMMUNICATION AND COMPUTER TECHNOLOGIES en-US Journal of VLSI Circuits and Systems 2582-1458 https://vlsijournal.com/index.php/vlsi/article/view/252 <p>An Arithmetic Logic Unit (ALU) is the core component for any processing unit to perform arithmetical and logical operations for modern computing. The design for ALUs for specific tasks including integer and floating-point arithmetic, logical operations, data movement, and control functions&nbsp; influences the CPU architecture and digital system design. This work presents a unified ALU implemented in Verilog hardware description language (HDL), capable of performing arithmetic and logic operations across diverse numerical representations. The ALU is engineered to integrate logic unit, signed arithmetic processor, unsigned arithmetic processor, and floating-point arithmetic processor. The selection of operation is governed by select line signals to facilitate versatile user-driven functionality at the hardware level. To enhance the computational efficiency for handling multiplication of 64-bit signed and unsigned operands which generates 128-bit result, the proposed ALU architecture employs parallelism by processing the most significant and least significant bits simultaneously. A flexible mechanism for selective output enables the user to extract the desired segment of the result. Consolidating floating-point and fixed-point computations within a single ALU instance, the proposed architecture reduces the silicon area with reduced power dissipation and computational latency while streamlining routing complexities. This multi-modal ALU design with high-throughput is particularly suited for deployment in heterogeneous computing environments such as general-purpose processors, cryptographic accelerators, and machine intelligence hardware, where the rapid processing of heterogeneous data types is essential for workload optimization and energy-efficient system operation.</p> Shilpi Birla Neha Singh Jeevani G.S.N Renu Kumawat Avireni Srinivasulu Copyright (c) 2025 Journal of VLSI Circuits and Systems 2025-11-05 2025-11-05 7 2 1 8 10.31838/JCVS/07.02.01