https://vlsijournal.com/index.php/vlsi <p>The <em>Journal of VLSI Circuits and Systems</em> is a peer-reviewed journal committed to publishing high-impact research in the field of Very-Large-Scale Integration (VLSI) design and systems engineering. The journal provides a platform for disseminating cutting-edge innovations that span the full spectrum of theoretical advances, simulation models, architecture design, physical implementations, and system-level integration in VLSI technology. (ISSN - 2582-1458)</p> <p>The journal invites original research papers, reviews, and application-driven studies that explore novel methodologies, tools, and trends across digital, analog, mixed-signal, and RF integrated circuits, as well as embedded and neuromorphic systems.</p> <p><strong>The journal covers a broad spectrum of topics related to VLSI circuits and systems, including but not limited to:</strong></p> <ol> <li><strong> VLSI Circuit Design</strong></li> </ol> <ul> <li>Low-power, high-speed digital circuit design methodologies.</li> <li>Analog and mixed-signal integrated circuits (ADC/DACs, PLLs, oscillators).</li> <li>Emerging logic families: adiabatic, quantum-dot cellular automata (QCA), reversible logic.</li> <li>Radiation-hardened and fault-tolerant circuit design.</li> <li>Clocking strategies, synchronization circuits, and time-interleaved designs.</li> </ul> <ol start="2"> <li><strong> Design Automation and EDA Tools</strong></li> </ol> <ul> <li>Hardware Description Languages (HDL), High-Level Synthesis (HLS), and Register Transfer Level (RTL) design.</li> <li>Placement, routing, and layout optimization.</li> <li>Logic and physical synthesis for power, performance, and area (PPA).</li> <li>AI/ML-driven EDA and design space exploration.</li> <li>Formal verification, equivalence checking, and constraint-driven simulation.</li> </ul> <ol start="3"> <li><strong> VLSI System Architectures</strong></li> </ol> <ul> <li>System-on-Chip (SoC), Network-on-Chip (NoC), and Chiplet-based modular architectures.</li> <li>Hardware/software co-design and hardware accelerators for edge and cloud computing.</li> <li>Memory subsystems: SRAM, DRAM, eNVM, MRAM, ReRAM integration.</li> <li>Application-specific architectures for AI, DSP, cryptography, and bioinformatics.</li> </ul> <ol start="4"> <li><strong> Emerging Trends and Technologies</strong></li> </ol> <ul> <li>3D ICs, Through-Silicon Vias (TSVs), and heterogeneous integration.</li> <li>Neuromorphic, brain-inspired, and spiking neural network hardware.</li> <li>Quantum VLSI circuits and cryo-CMOS design challenges.</li> <li>Photonic and plasmonic interconnects and optical VLSI.</li> <li>Approximate computing and in-memory computation (IMC).</li> </ul> <ol start="5"> <li><strong> Hardware Security and Reliability</strong></li> </ol> <ul> <li>Secure VLSI design, side-channel attack mitigation, and logic obfuscation.</li> <li>Hardware Trojans, counterfeit detection, and Physically Unclonable Functions (PUFs).</li> <li>Process variation analysis, aging-aware design, and reliability enhancement techniques.</li> <li>Design-for-testability (DFT), built-in self-test (BIST), and fault modeling.</li> </ul> <ol start="6"> <li><strong> AI and Reconfigurable VLSI Systems</strong></li> </ol> <ul> <li>FPGA/ASIC implementations of deep neural networks, transformers, and edge-AI.</li> <li>Real-time processing using dynamic partial reconfiguration.</li> <li>Hardware-aware neural architecture search (NAS) and pruning techniques.</li> <li>Custom tensor processors and systolic arrays for AI/ML inference and training.</li> </ul> <ol start="7"> <li><strong> Applications and Benchmarking</strong></li> </ol> <ul> <li>VLSI solutions for biomedical implants, autonomous vehicles, IoT, AR/VR, and robotics.</li> <li>Edge-computing accelerators with ultra-low power constraints.</li> <li>Energy-harvesting and battery-less VLSI systems.</li> <li>Benchmarking methodologies for performance, energy-efficiency, and silicon area.</li> </ul> <p>The journal targets academic researchers, VLSI designers, industry professionals, and students, aiming to advance VLSI circuit and system design through high-quality research.<br /><br /><strong>Frequency</strong> - 2 issue Per Year<br /><strong>ISSN</strong> - 2582-1458</p> SOCIETY FOR COMMUNICATION AND COMPUTER TECHNOLOGIES en-US Journal of VLSI Circuits and Systems 2582-1458 https://vlsijournal.com/index.php/vlsi/article/view/245 <p>High-speed memories like TCAM (Ternary Content Addressable Memory) are widely employed in highthroughput search applications like network routers. Using ASIC (Application-Specific Integrated Circuits) to construct TCAM memories allows for a higher search rate at the expense of increased power and resource requirements. However, safeguarding the TCAM from soft errors while maintaining good search speed and minimizing critical path time is a difficult task. In this paper, we present a TCAM architecture with a multipumping technique that incorporates the correction of multiple bits using the Hamming code. Different sizes, such as 4x4, 16x8 and 32x16, of the proposed TCAM architecture are simulated and implemented in 45nm technology. The proposed work evaluates<br />the TCAM in comparison to the Look-Up Table (LUT) based on a priority encoder in TCAM architecture, Two-Dimensional (2D) parity, Three-Dimensional (3D) parity, and Hamming code-based error correction methods with a multiplexer block in TCAM architecture. The results demonstrate that the suggested TCAM has a lesser delay compared to the LUT-based and higher error<br />correction capability, including the parity bits.</p> Sirisha Mallaiah M Vinodhini Copyright (c) 2025 Journal of VLSI Circuits and Systems 2026-02-26 2026-02-26 8 1 1 8 10.31838/JCVS/08.01.01 https://vlsijournal.com/index.php/vlsi/article/view/291 <p>The physical design phase of Very-Large-Scale-Integration (VLSI) is notoriously difficult since it must strike a balance between PPA, power, and performance. Computationally costly design cycles and less-than-ideal Pareto fronts are common challenges of using traditional optimization methods to tackle these metrics in order. As part of physical design, this study suggests a new reinforcement learning (RL) framework that can optimize all three PPA measures in real time. In the proposed method, commercial electronic design automation (EDA) tools were used in conjunction with a deep deterministic policy gradient (DDPG) agent to make routing and placement decisions incrementally. Guided by a customized reward function that dynamically balances PPA trade-offs based on design stage priorities, the agent operates on a continuous action space that represents geometric coordinates and constraint modifications. While conventional sequential optimization methodologies reduce optimization runtime by about 35%, the proposed RL agent improves the power-performance product by 18.7% and the area reduction by 12.3%, according to simulation results on the ISPD 2015 benchmark suite. An innovative approach to optimize intelligent, adaptable physical designs that successfully traverse the high-dimensional PPA trade-off space is presented by the suggested framework.</p> Hussain Ali Mutar Ibtihal Razaq Niama ALRubeei Omar Hashim Yahya Naseer Ali Hussien Haider TH. Salim AlRikabi Abdul Hadi M. Alaidi Copyright (c) 2026 Journal of VLSI Circuits and Systems 2026-02-26 2026-02-26 8 1 9 19 10.31838/JCVS/08.01.02