Journal of VLSI Circuits and Systems

Development of Synthesizable Filter-Centric Loop Filter Design for ADPLL Architecture in SoC

Ravikumar G — 2024-06-28

The emergence of all-digital phase-locked loop (ADPLL) filters marks a major advancement in the field of signal processing technology. These filters are engineered to align the phase and frequency of digital signals, ensuring accurate timing and accuracy in a wide range of applications. By using a digitally controlled oscillator (DCO) to adjust the frequency and compare it to a reference signal, ADPLL filters minimize phase differences, improve filtering efficiency, and reduce noise in digital communication systems. Due to their ability to adapt to different input signals and environmental factors, these filters are critical to modern electronic devices, especially in challenging applications such as wireless communications, data transmission, and clock synchronization. In this research work, the variable reset random walk filter is designed in ADPLL architecture. The complete ADPLL design is developed using Verilog HDL language and realized in Zynq 7000 all programmable SoC device. The resource and power utilization reports are compared with the existing ADPLL design. In other hands the Pk-to-Pk jitter and phase errors are compared, in all cases the proposed ADPLL design exhibits better performance compared to exiting ADPLL design.

Development of Low Power GNSS correlator in Zynq SoC for GPS and GLONSS

Arunalatha Botla — 2024-06-28

A low-power Global Navigation Satellite System (GNSS) correlator for GPS and GLONASS signals was developed using the Zynq System on Chip (SoC) technology. The main goal of this research was to create an efficient correlator that consumes minimal power while maintaining excellent signal processing capabilities. The proposed correlator architecture leverages the programmable logic and processing capabilities of the Zynq SoC, employing a combination of hardware and software implementations to achieve maximum power efficiency.The design of the GNSS correlator is implemented using Verilog, and the Verilog code is realized on the Zynq SoC device. To assess the resource utilization and power consumption of the proposed design, the Xilinx Vivado IDE is utilized for resource estimation and power analysis. Simulation results demonstrate the high precision of the low-power GNSS correlator in processing GPS and GLONASS signals.The findings of the study indicate significant power savings compared to conventional correlator designs. The proposed design enhances power utilization without compromising signal processing capabilities by utilizing optimizing the correlator architecture. The development of a low-power GNSS correlator facilitates the advancement of energy-efficient GNSS receiver designs, particularly for applications with limited power resources. The proposed architecture not only extends battery life but also simplifies the integration of GNSS positioning capabilities into devices with restricted power availability.

RoBA Multiplier-Driven FIR Filter Synthesis: Uniting Efficiency and Speed for Enhanced Digital Signal Processing

SATHWIK BANDI — 2024-07-25

Abstract —The main objective of this project includes, enhance the computational efficiency of DSP systems which make them operate more efficiently. Traditional DSP computations can be slow, so sometimes it's more important to be fast than completely accurate. To craft a Digital Signal Processor (DSP) systems even faster and save energy, researchers have designed circuits that approximate calculations, sacrificing a bit of precision. By this proposed solution, we designed a RoBA multiplier type for filters that rounds numbers to the closest whole number. By simplifying the multiplication process, this approximation reduces system’s size and speeds up the operation. Considering the fact that the multiplier typically functions at a slower pace compared to other components, this adjustment is anticipated to enhance the filter's overall efficiency. We compared the Vedic multiplier to the proposed ROBA multiplier. The acquired results showcase the power, area, number of slice LUTs, number of bonded Input/Output Buffers, and delay related to this multiplier and FIR filters were greatly decreased, while the multiplier speed increased proportionally.

Index Terms— Approximation multiplier, Energy-efficient computation, Accuracy trade-off, Performance evaluation, FIR filter, Multiplication strategies, Speed optimization.

A Novel Machine Learning Model for Early Detection of Advanced Persistent Threats Utilizing Semi-Synthetic Network Traffic Data

Ibrahim Nadim — 2024-08-01

Advanced Persistent Threats are not merely a buzzword, these highly sophisticated and stealthy cyber threats are characterized by their ability to infiltrate and persistently operate within target systems for extended periods, often remaining undetected until significant damage has been done. APTs have emerged as a formidable adversary, and it frequently attack important infrastructure, government entities, and private businesses. This research paper embarks on an examination of APTs, shedding light on their characteristics and strategies. The proposed model APTGuard in the paper presents vital way to detect and counter this menace effectively, employing a methodology that involves utilizing a Semi-Synthetic dataset using 6.8 Million samples of processed network flows for training and testing. Orchestrating four pivotal phases: data collection, feature selection, data pre-processing and applying of machine learning algorithms. Encompassing the application of the algorithms: long short-term memory (LSTM), logistic regression (LR), support vector machine (SVM), and k-nearest neighbours (KNN), with comparing the results, the paper emphasizes that APT Guard, achieves a notable accuracy of 99.89 % using 83 features. The paper makes a substantial contribution to create effective method for detecting and resist hidden and malicious APTs

Low Power System on Chip Implementation of Adaptive Intra Frame and Hierarchical Motion Estimation in H.265

T M Praneeth Naidu — 2024-08-01

Over the years, video compression standards have evolved and helped distribute multimedia content with greater ease. H.265 or High Efficiency Video Coding (HEVC) is one of the best lossy video codecs released as successor to H264 which offers better compression. This analysis is focused on tackling the computation needs of H.265 encoding through System on Chip (SoC) based implementations. The SoC platform has both ARM and FPGA architectures to handle floating point and fixed-point operations with parallelism respectively. The intended methodology is implemented using adaptive intra-frame prediction and hierarchical motion estimation suitable for SoC implementation to bridge the current gap. The innovation of this approach is that the parallel processing capabilities built into SoCs are used to improve intra-frame prediction and motion estimation efficiency. This proposed method involves the adaptive mechanisms for intra-frame prediction as well as a hierarchical structure of motion estimation to balance computational load and resource consumption. In conventional intra prediction, all the 35 modes are implemented, and the best mode is selected based on the Sum of Absolute Difference (SAD) value. In SoC this process can be implemented in parallel by using non-blocking modules for all the 35 modes. In order to improve the efficiency further, edge detection and content analysis modules are added to analyse the blocks before the modes are selected. This make sures that only required modes are executed based on the content that is present in the block. The traditional motion estimation module is improved by adding a hierarchical framework to select the best matching block more effectively. To solve the power consumption problems, Intelligent Clock Gating (ICG) is applied in order to switch off idle modules and hence reduce dynamic power consumption drastically. This low-power optimization results in extended operation times for portable devices while minimizing thermal footprint. The proposed methodology successfully improved the overall efficiency of the H.265 framework.

Design of Novel High Speed Energy Efficient Robust 4:2 Compressor

Anju Rajput — 2024-08-27

Multipliers are crucial in deciding the overall efficiency of the arithmetic circuits. Compressors are one of the vital components of the multipliers. This paper presents a new architecture for a 4:2 compressor, utilizing a novel truth table as well as internal equations. Additionally, the research investigates the methodology to incorporate a fast compressor into the XOR-XNOR circuit framework. Significantly, the suggested design has fewer transistors as compared to the existing 4:2 compressors. Four different and existing 4:2 compressors are examined closely for the comparative analysis with the proposed circuit. The suggested structure is compared with the latest ones found in modern publications, considering the power usage, latency as well as space optimization along with the Monte Carlo and Corner analysis. The proposed compressor has 49% lesser delay, 53% lower Power Delay Product and 76.27% lesser Energy Delay Product than the other prevailing compressor designs. Architecture simulation is performed using Cadence Virtuoso tool in 45 nanometer CMOS technology with power supply of 1 volt.