Unified Multimodal 64-Bit Arithmetic Logic Unit for High-Performance Computing Architectures

Shilpi Birla, Neha Singh, Jeevani G.S.N, Renu Kumawat, Avireni Srinivasulu — Wed, 05 Nov 2025 00:00:00 +0300

An Arithmetic Logic Unit (ALU) is the core component for any processing unit to perform arithmetical and logical operations for modern computing. The design for ALUs for specific tasks including integer and floating-point arithmetic, logical operations, data movement, and control functions influences the CPU architecture and digital system design. This work presents a unified ALU implemented in Verilog hardware description language (HDL), capable of performing arithmetic and logic operations across diverse numerical representations. The ALU is engineered to integrate logic unit, signed arithmetic processor, unsigned arithmetic processor, and floating-point arithmetic processor. The selection of operation is governed by select line signals to facilitate versatile user-driven functionality at the hardware level. To enhance the computational efficiency for handling multiplication of 64-bit signed and unsigned operands which generates 128-bit result, the proposed ALU architecture employs parallelism by processing the most significant and least significant bits simultaneously. A flexible mechanism for selective output enables the user to extract the desired segment of the result. Consolidating floating-point and fixed-point computations within a single ALU instance, the proposed architecture reduces the silicon area with reduced power dissipation and computational latency while streamlining routing complexities. This multi-modal ALU design with high-throughput is particularly suited for deployment in heterogeneous computing environments such as general-purpose processors, cryptographic accelerators, and machine intelligence hardware, where the rapid processing of heterogeneous data types is essential for workload optimization and energy-efficient system operation.

VLSI Circuits–Oriented Gate-Length-Dependent DC–RF Compact Modeling of AlInN/AlN/GaN MISHEMTs with SSEC Extraction

K. Nagabushanam, Sriadibhatla Sridevi — Fri, 26 Dec 2025 00:00:00 +0300

This work develops a compact analytical DC-RF model based on VLSI-circuit design that accounts for gate-length scaling impacts in RF circuit designs using . In order to effectively simulate the drain current density, transconductance and the gate charge for use in simulating RF and microwaves circuits using technology, a two-dimensional electron gas (2-D) sheet-charge based formulation has been developed to account for flat-band voltage and polarization charge impacts. This model was validated with both TCAD simulations and experimental data for a range of gate lengths (from 0.1 to 0.3 μm), resulting in a maximum drain current density of 2.35 A/mm and an estimated cut of frequency of125 GHz when the gate length was 0.1 μm. In addition, a refined small-signal equivalent circuit (SSEC) extraction methodology, integrating conventional and gradient-based optimization techniques, is introduced to improve parasitic de-embedding accuracy. Extracted S-parameters enable robust frequency-domain characterization, yielding f_T=170 GHz and f_max=183 GHz. The proposed compact model demonstrates scalable, bias-consistent DC and RF prediction, making it well suited for VLSI RF and microwave circuit design and simulation using GaN MISHEMT technologies.

Journal of VLSI Circuits and Systems

Unified Multimodal 64-Bit Arithmetic Logic Unit for High-Performance Computing Architectures

VLSI Circuits–Oriented Gate-Length-Dependent DC–RF Compact Modeling of AlInN/AlN/GaN MISHEMTs with SSEC Extraction