Journal of VLSI Circuits and Systems

Physics-Informed VLSI TinyML-Based Self-Healing PLL with Power–Jitter Optimization Under Aging and PVT Variations

Tue, 08 Sep 2026 00:00:00 +0200

Phase-locked loops (PLLs) are essential components for generating frequency signals in today’s systems on a chip, but their overall jitter, stability, and behavior in terms of being ‘locked’ to each other can be affected by the varied manufacturing process, operating
voltage, and temperature, and long-term aging of the devices as well as other factors (e.g., supply chain issues, etc.). PLLs use feedback to regulate the output frequency, and any of the aforementioned types of variability can result in less-than-optimal characteristics
(e.g., loop gain, VCO sensitivity, charge pumps, etc.), thus causing PLLs to drift away from the intended damping and bandwidth; therefore, increasing RMS jitter or forcing conservative guard banding that wastes power. Recent research has demonstrated the continued development of PLL architectures/calibration techniques and how critical it is that, as semiconductor technology continues to scale down, sufficient attention will be paid to ensuring that the PLL user’s dynamic performance remains robust, given the continued variability and reliability issues associated with technology scaling. Additionally, studies on aging have shown that mechanisms like BTI have measurable effects on charge pump operation, underscoring the need for lifetime-based compensation methods rather than fixed margins. This study proposes a physics-informed TinyML self-healing PLL that utilizes (i) on-chip monitors, (ii) a compact TinyML estimator to provide a near-optimal initial knob setting, and (iii) a constrained local refinement stage that enforces power budgets and stability/transient constraints expressed through ζ, wn, resonant peaking Mr, and settling time ts. We formulate runtime tuning as a constrained multi-objective optimization over ICP and loop bandwidth BW. A simulation-centered evaluation using a behavioral CP-PLL model augmented with stochastic PVT spread and aging degradation spans T ∈ [–20,100]ºC, VDD ∈ [0.85, 1.15]V, and aging a ∈ [0, 7] years will be performed with the goal of demonstrating that the proposed method will achieve a significant and consistent reduction in jitter across 1200 random operating conditions for the represented device under the constraints
imposed and enforced; conversely, it will be demonstrated that jitter reduction based purely on TinyML decision making will have nonzero violations related to the constraints imposed. The results of the evaluation will demonstrate the practicality of using compact
learning in combination with physics-based feasibility checks to achieve predictable self-healing behavior suitable for VLSI clocking subsystems.

A Low Power and Area Efficient Leading Zero Counter

N. Hemanth, Sonali Agrawal, M. Vinodhini — Tue, 08 Sep 2026 00:00:00 +0200

The latest and up-to-date arrangements for arithmetic logic units are necessary for modern processors to function effectively. Leading zero counters (LZCs) are indispensable for floating-point operations because they accelerate computational throughput and allow for
parallel processing. Advancements in ASIC technology have enabled the development of LZC systems that process information rapidly and use very little energy. The high-speed, energy-efficient performance of Application Specific Integrated Circuits (ASICs) is why they
are preferred for creating LZCs in modern computer systems. By reducing the number of transistors required, the proposed LZC architecture results in smaller area and power consumption than other embedded multiplier designs. Of the four techniques, the 32-bit
LZC results in a 28.72% space reduction and a 16.44% decrease in power consumption. Similar to 64-bit LZC, the design achieves a 27.65% reduction in area and a 21.64% reduction in power consumption. These changes cause only a small increase in delay compared
to LZC done in the past. The design was implemented using Verilog Hardware Description Language (HDL) and processed using the Xilinx Vivado application on the 45 nm technology node. Consequently, the architecture is scalable and easily adapted to modern processing requirements. This architecture significantly reduces energy consumption, contributing to energy-efficient computing systems and supporting sustainable digital infrastructure.

Generalization-Aware Evaluation of HLS QoR Prediction: In-Distribution Performance versus Cross-Algorithm Generalization Using ForgeHLS

Ameen Shaheen, Wael Alzyadat, Aysh Alhroob — Tue, 08 Sep 2026 00:00:00 +0200

High-Level Synthesis (HLS) enables efficient FPGA-based accelerator design, but quality-of-results (QoR) exploration remains expensive because accurate latency and resource estimates typically require full synthesis flows. This has motivated the use of machine
learning (ML) for early QoR prediction. However, it remains unclear whether strong performance under conventional random train/test splits truly reflects generalization to unseen algorithms. In this work, we study this question using the ForgeHLS design-level dataset. We build a reproducible multitarget QoR prediction pipeline to estimate six metrics: BRAM, LUT, DSP, FF, best-case latency, and worst-case latency. To isolate the effect of the evaluation protocol, we adopt a simple and interpretable Random Forest baseline and evaluate it under two settings: a standard random split and a stricter group split based on algorithm identity. In addition, a boosting-based baseline (XGBoost) is evaluated to verify that the observed behavior is not model-specific. We further repeat the group-based evaluation across multiple random seeds. The results show that the baseline performs strongly under random splitting, especially for BRAM and latency-related targets, but that its performance degrades sharply under group-based evaluation. Repeated group-split experiments confirm that this degradation is systematic rather than incidental. Feature importance analysis further indicates that the strongest predictive signals are closely tied to algorithm identity and source-related information. Overall, the study shows that random-split evaluation can substantially overestimate the true capability of HLS QoR predictors and underscores the importance of generalization-aware evaluation protocols for future ML-based HLS QoR prediction research.