High Speed and Efficient Wallace Tree Multiplier for Dsp Applications

Abstract

Multiplier is one of the key and fundamental block in the many applications such as DSP, signal processing etc. In numerous occasions multipliers plays a prominent role to decide the system performance. Out of the several multipliers wallace tree multiplier is one of reliable and occupies the minimal space in digital applications. This work describes the designing of the high performance 8 bit wallace tree multiplier using compressor technique. The multiplier were simulated and estimated its performance using the Vivado.