ASIC Implementation of An Effective Reversible R2B Fft for 5G Technology Using Reversible Logic

Abstract

In recent times, 5G technology is an emerging advancement in the communication system. Because of its improved properties such as bandwidth, speed, connectivity etc., it has various applications in different areas. To acquire these properties in communication systems, the internal architecture for transmission and reception must be advanced. In early generations, irreversible logic gates with CMOS technology were used for FFT (Fast Fourier Transform) implementation, an essential aspect of communication. The primary concern of using irreversible gates is the increased complexity and power consumption. Another concern is heat dissipation due to reduced area of the chip (or chip size), because of which there is some loss of information during transmission. These fundamental causes can be resolved entirely by using reversible logic, which consumes less power, provides high performance and speed, and has
low heat dissipation. This paper describes an Application-specific Integrated Circuit (ASIC) implementation of reversible Radix 2 Butterfly (R2B) FFT using reversible logic effectively. Reversible R2B FFT as a whole (i.e., both forward and reverse FFT) utilises
reversible adder/ subtractor (both half adder (RH) and full adder (RF)) and reversible multiplier instead of generic combinational circuits. The design procedure is using Xilinx 14.2i for simulation and synthesis of Reversible R2B FFT.