Adaptive And Recursive Vedic Karatsuba Multiplier Using Non Linear Carry Select Adder

Abstract

Multipliers play a vital role in any applications like signal processing, image processing, floating-point processors etc. These applications require efficient binary multiplications, but it is most powerful as well as time consuming process. An efficient binary
multiplication is proposed to reduce the delay. Vedic Karatsuba multiplier is an efficient algorithm which can be used to reduce the delay. The combination of adaptive and recursive approach of Vedic Karatsuba algorithm along with Non - Linear Carry Select Adder is implemented to get the better results. Multiplier designs are coded in Verilog by using Xilinx software