Hardware/Software Co-Design using ZYNQ SoC

Abstract

A Programmable Logic (PL) (FPGA) and Processing Subsystem (PS) (ARM Cortex-A9) make up the Xilinx ZYNQ-7000 SoC.. The data transfer arrangement between the PL and PS is an important part of the ZYNQ Architecture. In comparison to other existing solutions, the AXI Interconnect serves as a vital communication link between PL and PS for bi-directional data transfer. This paper explores configuration between the PL and PS with in the ZYNQ-7000 SoC. Implemented a logic with configuration of both PS and PL and only PL.