ESTIMATION OF RELIABILITY OF D FLIP-FLOPS USING MC ANALYSIS

Abstract

As the day by day size of the electronic devices has been decreased by scaling down the of the VLSI technology. For any electronic devices reliability is one of the best performance indicator which decides the life time of the any device. In this paper we investigated the performance of thelow power edge triggered d flip flop and dual edge triggered static pulsed flip-flop respectively. Simulated the given circuit in cadence virtuoso environment using the 180 nm technology. To estimate the reliability we used the Monte Carlo analysis and applied at different corners such as SS,SF,FS,FF and TT respectively.