HIGH SPEED AND RELIABLE DOUBLE EDGE TRIGGERED D- FLIP-FLOP FOR MEMORY APPLICATIONS

Abstract

In this paper we designed a low power and high speed phase detector using the positive edge triggered D flip flop. the proposed architecture consists of the 16 number of transistors and it consumes the very less power 10.25uw with the phase noise -150.45db respectively with offset frequency of 1Mhz. The circuit also tested the different corners in order to analyse the reliability of the circuit(TT,FF,SS.SF,FS) respectively.