DESIGN OF THE HIGH SPEED AND RELIABLE SOURCE COUPLED LOGIC MULTIPLEXER

Abstract

As the rapid growth of the VLSI technology over the years the momentum shifts towards the low power and high speed portable electronic devices respectively. Power consumption is one critical aspect which may leads to decreases the reliability and performance of the portable devices. the main aim of this work is to design a low power and high speed Source Coupled Logic (SCL) multiplexer and its analytical model. This circuits can be widely used in mixed signal circuits and high resolution optical fiber links.the proposed circuit was implemented in CMOS 45 nm technology using cadence virtuoso by using industrial technology libraries. And we compared its performances with the existed configurations of the multiplexers with different technology