Development of Synthesizable Filter-Centric Loop Filter Design for ADPLL Architecture in SoC

Abstract

The emergence of all-digital phase-locked loop (ADPLL) filters marks a major advancement in the field of signal processing technology. These filters are engineered to align the phase and frequency of digital signals, ensuring accurate timing and accuracy in a wide range of applications. By using a digitally controlled oscillator (DCO) to adjust the frequency and compare it to a reference signal, ADPLL filters minimize phase differences, improve filtering efficiency, and reduce noise in digital communication systems. Due to their ability to adapt to different input signals and environmental factors, these filters are critical to modern electronic devices, especially in challenging applications such as wireless communications, data transmission, and clock synchronization. In this research work, the variable reset random walk filter is designed in ADPLL architecture. The complete ADPLL design is developed using Verilog HDL language and realized in Zynq 7000 all programmable SoC device. The resource and power utilization reports are compared with the existing ADPLL design. In other hands the Pk-to-Pk jitter and phase errors are compared, in all cases the proposed ADPLL design exhibits better performance compared to exiting ADPLL design.