Vol. 6 No. 2 (2024): Current issue

Published: 2024-06-28

Articles

Development of Synthesizable Filter-Centric Loop Filter Design for ADPLL Architecture in SoC

Ravikumar G, Venkatareddy D, Asharani M

1-13
- PDF
Development of Low Power GNSS correlator in Zynq SoC for GPS and GLONSS

Arunalatha Botla, Kanaka Durga G, Chandrasekhar Paidimarry

14-22
- PDF
RoBA Multiplier-Driven FIR Filter Synthesis: Uniting Efficiency and Speed for Enhanced Digital Signal Processing

Sathwik Bandi; D.Sudha, Y Aruna Suhasini Devi , Jagadeesh Bodapati

23-30
- PDF
A Novel Machine Learning Model for Early Detection of Advanced Persistent Threats Utilizing Semi-Synthetic Network Traffic Data

Nadim Ibrahim, N.R. Rajalakshmi, Karam Hammadeh

31-39
- PDF
Low Power System on Chip Implementation of Adaptive Intra Frame and Hierarchical Motion Estimation in H.265

T M Praneeth Naidu, P. Chandra Sekhar, Pradeep Kumar Boya

40-52
- PDF
Design of Novel High Speed Energy Efficient Robust 4:2 Compressor

Anju Rajput, Renu Kumawat, Jyoti Sharma, Avireni Srinivasulu

53-64
- PDF
Transforming Economic Development through VLSI Technology in the Era of Digitalization

Halyna Yaremko, Lesia Stoliarchuk, Liudmyla Huk, Maria Zapotichna, Halyna Drapaliuk

65-74
- PDF
Reversible Vedic Direct Flag Divider in Key Generation of RSA Cryptography

Udhayakumar A, Ramya K C, Vijayakumar P, Sheeba Rani S, Balamanikandan A, Saranya K

75-83
- PDF
Design and Performance Analysis of Adiabatic Logic Circuits Using FinFET Technology

Anas A. Salameh, Othman Mohamed

84-90
- PDF
Energy-Efficient High Speed Quantum-Dot Cellular Automata (QCA) based Reversible Full Adders for Low-Power Digital Computing Applications

Anas A. Salameh, Othman Mohamed

91-98
- PDF
VLSI-Based MED-MEC Architecture for Enhanced IoT Wireless Sensor Networks

T.Suguna, Rakesh Ranjan, A. Sai Suneel, V Raja Rajeswari, M.Janaki Rani, Richa Singh

99-106
- PDF
Implementation of VLSI Systems Incorporating Advanced Cryptography Model for FPGA-IoT Application

Anandhi S, Rajendrakumar R, T.Padmapriya, S.V. Manikanthan, Jeneetha Jebanazer J, J RajaSekhar

107-114
- PDF
VLSI architecture-based implementation of motion estimation algorithm for Underwater Robot Vision System

Aarti Hemant Tirmare, Priyadarshani Shivakumar Mali, Amardeep Anandrao Shirolkar, Ganesh Rajaram Shinde, Vikas Dattatray Patil, Hemant Appa Tirmare

115-121
- PDF
Thermometer Coding-Based Application-Specific Efficient Mod Adder for Residue Number Systems

Sarada Musala, Vijaya Vardhan K

122-129
- PDF

Vol. 6 No. 2 (2024): Current issue

Articles

Development of Synthesizable Filter-Centric Loop Filter Design for ADPLL Architecture in SoC

Development of Low Power GNSS correlator in Zynq SoC for GPS and GLONSS

RoBA Multiplier-Driven FIR Filter Synthesis: Uniting Efficiency and Speed for Enhanced Digital Signal Processing

A Novel Machine Learning Model for Early Detection of Advanced Persistent Threats Utilizing Semi-Synthetic Network Traffic Data

Low Power System on Chip Implementation of Adaptive Intra Frame and Hierarchical Motion Estimation in H.265

Design of Novel High Speed Energy Efficient Robust 4:2 Compressor

Transforming Economic Development through VLSI Technology in the Era of Digitalization

Reversible Vedic Direct Flag Divider in Key Generation of RSA Cryptography

Design and Performance Analysis of Adiabatic Logic Circuits Using FinFET Technology

Energy-Efficient High Speed Quantum-Dot Cellular Automata (QCA) based Reversible Full Adders for Low-Power Digital Computing Applications

VLSI-Based MED-MEC Architecture for Enhanced IoT Wireless Sensor Networks

Implementation of VLSI Systems Incorporating Advanced Cryptography Model for FPGA-IoT Application

VLSI architecture-based implementation of motion estimation algorithm for Underwater Robot Vision System

Thermometer Coding-Based Application-Specific Efficient Mod Adder for Residue Number Systems

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