Development of Low Power GNSS correlator in Zynq SoC for GPS and GLONSS

Abstract

A low-power Global Navigation Satellite System (GNSS) correlator for GPS and GLONASS signals was developed using the Zynq System on Chip (SoC) technology. The main goal of this research was to create an efficient correlator that consumes minimal power while maintaining excellent signal processing capabilities. The proposed correlator architecture leverages the programmable logic and processing capabilities of the Zynq SoC, employing a combination of hardware and software implementations to achieve maximum power efficiency.The design of the GNSS correlator is implemented using Verilog, and the Verilog code is realized on the Zynq SoC device. To assess the resource utilization and power consumption of the proposed design, the Xilinx Vivado IDE is utilized for resource estimation and power analysis. Simulation results demonstrate the high precision of the low-power GNSS correlator in processing GPS and GLONASS signals.The findings of the study indicate significant power savings compared to conventional correlator designs. The proposed design enhances power utilization without compromising signal processing capabilities by utilizing optimizing the correlator architecture. The development of a low-power GNSS correlator facilitates the advancement of energy-efficient GNSS receiver designs, particularly for applications with limited power resources. The proposed architecture not only extends battery life but also simplifies the integration of GNSS positioning capabilities into devices with restricted power availability.