Design of Novel High Speed Energy Efficient Robust 4:2 Compressor

Abstract

Multipliers are crucial in deciding the overall efficiency of the arithmetic circuits. Compressors are one of the vital components of the multipliers. This paper presents a new architecture for a 4:2 compressor, utilizing a novel truth table as well as internal equations. Additionally, the research investigates the methodology to incorporate a fast compressor into the XOR-XNOR circuit framework. Significantly, the suggested design has fewer transistors as compared to the existing 4:2 compressors. Four different and existing 4:2 compressors are examined closely for the comparative analysis with the proposed circuit. The suggested structure is compared with the latest ones found in modern publications, considering the power usage, latency as well as space optimization along with the Monte Carlo and Corner analysis. The proposed compressor has 49% lesser delay, 53% lower Power Delay Product and 76.27% lesser Energy Delay Product than the other prevailing compressor designs. Architecture simulation is performed using Cadence Virtuoso tool in 45 nanometer CMOS technology with power supply of 1 volt.