Design a Low Power and High-Speed Parity Checker using Exclusive–or Gates

Abstract

In the presented paper we designed the parity checkerby using EX-OR modules. The two EX-OR modules are presented to design the parity checker and correlated their outcomes based on the constraints like power, area, delay and power delay product (PDP). The previous design is with eight transistors EX-OR, but in the present six transistors EX-OR is used to design the parity checker. While correlating the parity checker design with 8T EX- OR and 6T EX-OR, the 6T EX-OR parity checker design gives optimized power, delay, area and PDP over the 8T EX-OR parity checker design. Simulations are done by using the 130nm mentor graphics tool. Finally, the constraints like power, area, delay and PDP gets optimized successfully with the presented technology. Also, alternatively we can replace EX- OR modules with NAND modules to design parity checker.