Vol. 3 No. 2 (2021): JVCS

Articles

• Design and Performance Analysis of High Speed 8-T Full Adder

  KOMMA YASASWI RAJ, GUNDU SAI VIPUL, GOTTIPATI RAVINDRA, RUDRU GOPI VENKATA KRISHNA, SADULLA SHAIK

  1-10

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• Design Of Clocked Jk Flip Flop Using Air Hole Structured Photonic Crystal

  K. MALLI KARJUNA RAO, NERELLA JHANSI ANEELA, KOTAPATI YAGNATEJA SRI, KONDA NAIMISHA PRASANNA, NALLAPU SAHITHI, LAVU LIKHITHA

  11-20

  • pdf

• Design Of Clocked Hybrid (D/T) Flipflop Through Air Hole Paradigm Photonic Crystal

  K. MALLIKARJUNA RAO, P.V.N. SAI BHARADWAJ, SHAIK MASTAN VALI, NANDA MAHESH, THOTA TEJA SAI

  21-33

  • pdf

• Energy Reduction of D-Flipflop Using 130nm CMOS Technology

  KOTHA GAYATHRI DEVI, KOTTAPALLI TEJASREE, MERUGUMALA KEZIA SWARNA SRI, MOPIDEVI PRAVALLIKA

  34-41

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• Design A Low Power and High Throughput 130nm Full Adder Utilising Exclusive-OR And Exclusive- NOR Gates

  SONIYA NUTHALAPATI, KUSUMA NUTALAPATI, KALAPALA RADHIKA RANI, LINGISETTY LOURDU SASIREKHA, SIRISHA MEKALA, FIRDOSIA PARVEEN MOHAMMAD

  42-47

  • pdf

• Design a Low Power and High-Speed Parity Checker using Exclusive–or Gates

  BRAHMAIAH BATTULA, PUTTA VIJAYA LAKSHMI, SANDINENI LAKSHMI NAVYA SRI, SUNANDA KARPURAPU, SIKHAKOLLI DURGA SRI SRAVYA

  48-53

  • pdf