Energy Reduction of D-Flipflop Using 130nm CMOS  Technology

KOTHA GAYATHRI DEVI; KOTTAPALLI TEJASREE; MERUGUMALA KEZIA SWARNA SRI; MOPIDEVI PRAVALLIKA

doi:10.31838/jvcs/03.02.04

Energy Reduction of D-Flipflop Using 130nm CMOS Technology

Authors

KOTHA GAYATHRI DEVI
KOTTAPALLI TEJASREE
MERUGUMALA KEZIA SWARNA SRI
MOPIDEVI PRAVALLIKA

DOI:

https://doi.org/10.31838/jvcs/03.02.04

Keywords:

D-flipflop, size, energy, transistor

Abstract

At present devices are being used widely. In every device there is use of large number of components. One of the major components in designing a device is a D- flipflop. The features and usage of every component is being increased rapidly. So, here we are going to reduce the size (transistor count), energy (power consumption and power delay) of a D-flipflop.

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Published

2021-10-05

How to Cite

KOTHA GAYATHRI DEVI, KOTTAPALLI TEJASREE, MERUGUMALA KEZIA SWARNA SRI, & MOPIDEVI PRAVALLIKA. (2021). Energy Reduction of D-Flipflop Using 130nm CMOS Technology. Journal of VLSI Circuits and Systems, 3(2), 34–41. https://doi.org/10.31838/jvcs/03.02.04