A Low Power Adiabatic Approach for Scaled VLSI Circuits

Authors

  • Dr. Abhishek Bhattacharjee Dr.
  • Dr. Tanmoy Majumder Dr.
  • Sabarni Bhowmik Mrs.

DOI:

https://doi.org/10.31838/jvcs/06.01.01

Keywords:

Adiabatic logic, low power, phase-shifted clock, two-phase clock, power clock generator

Abstract

Two Phase Clocked Adiabatic Static CMOS Logic(2PASCL) approach is proposed as an efficient power reduction technique in this work to reduce the overall power consumption of any VLSI circuit. One of the most significant area of research in today's VLSI domain is power reduction. By using a complementary phase-shifted voltage source, we can minimize the charging-discharging of the load capacitor in each clock pulse, which plays a vital role in reducing the circuits' dynamic power consumption.

 

 

Author Biographies

Dr. Abhishek Bhattacharjee, Dr.

Assistant Professor, Department of Electronics and Communication Engineering, Tripura Institute of Technology, Narsingarh

Dr. Tanmoy Majumder, Dr.

Assistant Professor, Department of Electronics and Communication Engineering, TIT Narsingarh

Sabarni Bhowmik, Mrs.

M.tech Research Scholar, Department of Electronics and Communication Engineering, TIT Narsingarh

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Published

2023-12-06

How to Cite

Abhishek Bhattacharjee, Tanmoy Majumder, & Sabarni Bhowmik. (2023). A Low Power Adiabatic Approach for Scaled VLSI Circuits. Journal of VLSI Circuits and Systems, 6(1), 1–6. https://doi.org/10.31838/jvcs/06.01.01

Issue

Vol. 6 No. 1 (2024): JVCS

Section

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