Vol. 6 No. 1 (2024): JVCS

Articles

• A Low Power Adiabatic Approach for Scaled VLSI Circuits

  Dr. Abhishek Bhattacharjee, Dr. Tanmoy Majumder, Sabarni Bhowmik

  1-6

  • pdf

• Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

  Pakkiraiah C, R.V.S. Satyanarayana

  7-18

  • pdf

• 1.8-V Low Power, High-Resolution, High-Speed Comparator With Low Offset Voltage Implemented in 45nm CMOS Technology

  Ishrat Zahan Mukti, Ebadur Rahman Khan, Koushik Kumar Biswas

  19-24

  • pdf

• Low Power Embedded SoC Design

  G. Sasikala, G. Satya Krishna

  25-29

  • pdf

• Desing of VLSI Architecture for a flexible testbed of Artificial Neural Network for training and testing on FPGA

  Gurmeet Arora

  30-35

  • pdf

• A Hybrid Optical-Acoustic Modem Based on MimoOfdm for Reliable Data Transmission in Green Underwater Wireless Communication

  pallavi ch, G. Sreenivasulu

  36-42

  • pdf

• Detection Of Soft Errors in Clock Synthesizers and Latency Reduction Throgh Voltage Scaling Mechanism

  Mohamed Arshath

  43-50

  • pdf

• Smart Ways to Catch the Abutment DRCs at IP Level

  Ravi N, Swanand Kulkarni

  51-54

  • pdf

• Design and VLSI implementation of SAR Analog to Digital Converter Using Analog Mixed Signal

  Megha N, Prajwal Shetty, Rahul R Kudtarkar, Siddesh U Naik, A L Abhilash

  55-60

  • pdf

• Low Power SoC based Road Surface Crack Segmentation using Unet with Efficientnet-B0 Architecture

  Radhika Reddy Kondam, P. Chandra Sekhar, Pradeep Kumar Boya

  61-69

  • PDF

• Design and Optimization of a High-Speed VLSI Architecture for Integrated FIR Filters in Advanced Digital Signal Processing Applications

  Wiki Lofandri, C. Selvakumar, Basant Sah, M. Sangeetha, Beulah Jabaseeli. N

  70-77

  • PDF