Detection Of Soft Errors in Clock Synthesizers and Latency Reduction Throgh Voltage Scaling Mechanism

Abstract

In the emerging growth of digital systems, the role of developing self-repairing circuits are demandable. Error tolerance is highly important for such automated platforms to perform well. The heart of any digital system rely on the clock signals opted for overall operation and synchronization. Soft errors in clock signal are serious issues. The proposed work considers the challenges of soft error occurrences in digital circuits such as radiation impact, latency errors, and employ the dual voltage scaling mechanism. The CMOS Schmitt trigger is initially developed with that an voltage scaling mechanism is created. The inputs voltage is varied using the voltage sweep circuit. For a frequency of 5MHz to 5 GHz is considered as the sweep frequency. The step size of sweep frequency is 500KHz. The parameters such as drain voltage (Vd), Source voltage (Vs) are controlled during the process and Gate-Source capacitance and Gate-Drain capacitance is measured. For the sweep frequency the stable clock outputs are generated from the proposed clock synthesizer (CS). The reduction of 0.018 ns of delay latency is achieved at 5GHz input.